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TMS320C6421 датащи(PDF) 1 Page - Texas Instruments

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номер детали TMS320C6421
подробное описание детали  Fixed-Point Digital Signal Processor
PDF  59 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
Logo TI - Texas Instruments

TMS320C6421 датащи(HTML) 1 Page - Texas Instruments

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1
TMS320C6421 Fixed-Point Digital Signal Processor
1.1 Features
TMS320C6421
Fixed-Point Digital Signal Processor
SPRS346A – JANUARY 2007 – REVISED MARCH 2007
[Flexible Allocation]
• High-Performance Digital Signal Processor
–
512K-Bit (64K-Byte) L2 Unified Mapped
(C6421)
RAM/Cache [Flexible Allocation]
–
2.5-, 2.-, 1.67-ns Instruction Cycle Time
• Endianess: Supports Both Little Endian and
–
400-, 500-, 600-MHz C64x+™ Clock Rate
Big Endian
–
Eight 32-Bit C64x+ Instructions/Cycle
–
3200, 4000, 4800 MIPS
• External Memory Interfaces (EMIFs)
–
Fully Software-Compatible With C64x
–
16-Bit DDR2 SDRAM Memory Controller
With 128M-Byte Address Space (1.8-V I/O)
–
Commercial and Extended Temperature
Ranges
–
Asynchronous 8-Bit-Wide EMIF (EMIFA)
With up to 64M-Byte Address Reach
• VelociTI.2™ Extensions to VelociTI™
• Flash Memory Interfaces
Advanced Very-Long-Instruction-Word (VLIW)
• NOR (8-Bit-Wide Data)
TMS320C64x+™ DSP Core
• NAND (8-Bit-Wide Data)
–
Eight Highly Independent Functional Units
With VelociTI.2 Extensions:
• Enhanced Direct-Memory-Access (EDMA)
• Six ALUs (32-/40-Bit), Each Supports
Controller (64 Independent Channels)
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
• Two 64-Bit General-Purpose Timers (Each
Arithmetic per Clock Cycle
Configurable as Two 32-Bit Timers)
• Two Multipliers Support Four 16 x 16-Bit
• One 64-Bit Watch Dog Timer
Multiplies (32-Bit Results) per Clock
• One UART With RTS and CTS Flow Control
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
Results) per Clock Cycle
• Master/Slave Inter-Integrated Circuit
–
Load-Store Architecture With Non-Aligned
(I2C Bus™)
Support
• Multichannel Buffered Serial Port (McBSP0)
–
64 32-Bit General-Purpose Registers
–
I2S and TDM
–
Instruction Packing Reduces Code Size
–
AC97 Audio Codec Interface
–
All Instructions Conditional
–
SPI
–
Additional C64x+™ Enhancements
–
Standard Voice Codec Interface (AIC12)
• Protected Mode Operation
–
Telecom Interfaces – ST-Bus, H-100
• Exceptions Support for Error Detection
–
128 Channel Mode
and Program Redirection
• Multichannel Audio Serial Port (McASP0)
• Hardware Support for Modulo Loop
–
Four Serializers and SPDIF (DIT) Mode
Auto-Focus Module Operation
• 16-Bit Host-Port Interface (HPI)
• C64x+ Instruction Set Features
• 10/100 Mb/s Ethernet MAC (EMAC)
–
Byte-Addressable (8-/16-/32-/64-Bit Data)
–
IEEE 802.3 Compliant
–
8-Bit Overflow Protection
–
Supports Multiple Media Independent
–
Bit-Field Extract, Set, Clear
Interfaces (MII, RMII)
–
Normalization, Saturation, Bit-Counting
–
Management Data I/O (MDIO) Module
–
VelociTI.2 Increased Orthogonality
• VLYNQ™ Interface (FPGA Interface)
–
C64x+ Extensions
• Compact 16-bit Instructions
• Three Pulse Width Modulator (PWM) Outputs
• Additional Instructions to Support
• On-Chip ROM Bootloader
Complex Multiplies
• Individual Power-Savings Modes
• C64x+ L1/L2 Memory Architecture
• Flexible PLL Clock Generators
–
128K-Bit (16K-Byte) L1P Program
• IEEE-1149.1 (JTAG™)
RAM/Cache [Flexible Allocation]
Boundary-Scan-Compatible
–
128K-Bit (16K-Byte) L1D Data RAM/Cache
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
All trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the
Copyright © 2007–2007, Texas Instruments Incorporated
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.


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