AT89LS8252 datasheet(18/35 Pages) ATMEL

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AT89LS8252

0850C–MICRO–3/06

Program Memory Lock Bits

The AT89LS8252 has three lock bits that can be left unpro-

grammed (U) or can be programmed (P) to obtain the addi-

tional features listed in the following table.

When lock bit 1 is programmed, the logic level at the EA pin

is sampled and latched during reset. If the device is pow-

ered up without a reset, the latch initializes to a random

value and holds that value until reset is activated. The

latched value of EA must agree with the current logic level

at that pin in order for the device to function properly.

Once programmed, the lock bits can only be unpro-

grammed with the Chip Erase operations in either the par-

allel or serial modes.

Lock Bit Protection Modes (1) (2)

Notes:

1. U = Unprogrammed

2. P = Programmed

Program Lock Bits

Protection Type

LB1

LB2

LB3

No internal memory lock feature.

MOVC instructions executed from external program memory are disabled from fetching

code bytes from internal memory. EA is sampled and latched on reset and further

programming of the Flash memory (parallel or serial mode) is disabled.

Same as Mode 2, but parallel or serial verify are also disabled.

Same as Mode 3, but external execution is also disabled.

Programming the Flash and EEPROM

Atmel’s AT89LS8252 Flash Microcontroller offers 8K bytes

of in-system reprogrammable Flash Code memory and 2K

bytes of EEPROM Data memory.

The AT89LS8252 is normally shipped with the on-chip

Flash Code and EEPROM Data memory arrays in the

erased state (i.e. contents = FFH) and ready to be pro-

grammed. This device supports a High-Voltage (12V) Par-

allel programming mode and a Low-Voltage (2.7V to 6V)

Serial programming mode. The serial programming mode

provides a convenient way to download the AT89LS8252

inside the user’s system. The parallel programming mode

is compatible with conventional third party Flash or EPROM

programmers.

The Code and Data memory arrays are mapped via sepa-

rate address spaces in the serial programming mode. In

the parallel programming mode, the two arrays occupy one

contiguous address space: 0000H to 1FFFH for the Code

array and 2000H to 27FFH for the Data array.

The Code and Data memory arrays on the AT89LS8252

are programmed byte-by-byte in either programming mode.

An auto-erase cycle is provided with the self-timed pro-

gramming operation in the serial programming mode.

There is no need to perform the Chip Erase operation to

reprogram any memory location in the serial programming

mode unless any of the lock bits have been programmed.

In the parallel programming mode, there is no auto-erase

cycle. To reprogram any non-blank byte, the user needs to

use the Chip Erase operation first to erase both arrays.

Parallel Programming Algorithm

To program and verify the AT89LS8252 in the parallel pro-

gramming mode, the following sequence is recommended:

Power-up sequence:

Apply power between VCC and GND pins.

Set RST pin to “H”.

Apply a 3 MHz to 12 MHz clock to XTAL1 pin and wait

for at least 10 milliseconds.

Set PSEN pin to “L”

ALE pin to “H”

EA pin to “H” and all other pins to “H”.

Apply the appropriate combination of “H” or “L” logic

levels to pins P2.6, P2.7, P3.6, P3.7 to select one of

the programming operations shown in the Flash

Programming Modes table.

Apply the desired byte address to pins P1.0 to P1.7

and P2.0 to P2.5.

Apply data to pins P0.0 to P0.7 for Write Code opera-

tion.

Raise EA/V

PP to 12V to enable Flash programming,

erase or verification.

Pulse ALE/PROG once to program a byte in the

Code memory array, the Data memory array or the

lock bits. The byte-write cycle is self-timed and typi-

cally takes 1.5 ms.

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