AD8328

Rev. A | Page 7 of 20

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TOP VIEW

(Not to Scale)

20

19

18

17

16

15

14

13

12

11

1

2

3

4

5

6

7

8

9

10

AD8328

TXEN

SDATA

CLK

SLEEP

BYP

NC

NC = NO CONNECT

GND

GND

GND

GND

RAMP

GND

DATEN

GND

Figure 5. 20-Lead QSOP Pin Configuration

TOP VIEW

(Not to Scale)

AD8328

1

2

3

4

5

15

14

13

12

11

16

17

20 19 18

67

8

9 10

GND

GND

GND

RAMP

BYP

NC

Figure 6. 20-Lead LFCSP Pin Configuration

Table 5. 20-Lead QSOP and 20-Lead LFCSP Pin Function Descriptions

Pin No.

20-Lead

QSOP

Pin No.

20-Lead

LFCSP

Mnemonic

Description

1, 3, 4, 7,

11, 20

1, 2, 5, 9,

18, 19

GND

Common External Ground Reference.

2, 19

17, 20

Common Positive External Supply Voltage. A 0.1 μF capacitor must decouple each pin.

5

3

6

4

8

6

DATEN

Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register.

A Logic 0-to-Logic 1 transition transfers the latched data to the attenuator core (updates the gain)

and simultaneously inhibits serial data transfer into the register.

A Logic 1-to-Logic 0 transition inhibits the data latch (holds the previous gain state) and

simultaneously enables the register for serial data load.

9

7

SDATA

Serial Data Input. This digital input allows an 8-bit serial (gain) word to be loaded into the

internal register with the most significant bit (MSB) first.

10

8

CLK

Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit

master-slave register.

A Logic 0-to-Logic 1 transition latches the data bit, and a Logic 1-to-Logic 0 transfers the data bit

to the slave. This requires the input serial data-word to be valid at or before this clock transition.

12

10

SLEEP

Low Power Sleep Mode. In the sleep mode, the AD8328’s supply current is reduced to 20 μA.

13

11

NC

No Connect.

14

12

BYP

Internal Bypass. This pin must be externally ac-coupled (0.1 μF capacitor).

15

13

Negative Output Signal

16

14

Positive Output Signal

17

15

RAMP

External RAMP Capacitor (Optional)

18

16

TXEN

Logic 0 Disables Forward Transmission. Logic 1 enables forward transmission.