AD8331 datasheet(6/40 Pages) AD

6 / 40 page

AD8331/AD8332/AD8334

Rev. E | Page 6 of 40

Parameter

Conditions

Min

Typ

Max

Unit

ENABLE INTERFACE

(PIN ENB, PIN ENBL, PIN ENBV)

Logic Level to Enable Power

2.25

Logic Level to Disable Power

1.0

Input Resistance

Pin ENB

kΩ

Pin ENBL

kΩ

Pin ENBV

kΩ

Power-Up Response Time

VINH = 30 mV p-p

300

μs

VINH = 150 mV p-p

HILO GAIN RANGE INTERFACE (PIN HILO)

Logic Level to Select HI Gain Range

2.25

Logic Level to Select LO Gain Range

1.0

Input Resistance

kΩ

OUTPUT CLAMP INTERFACE

(PIN RCLMP; HI OR LO GAIN)

Accuracy

HILO = LO

RCLMP = 2.74 kΩ, VOUT = 1 V p-p (clamped)

±50

HILO = HI

RCLMP = 2.21 kΩ, VOUT = 1 V p-p (clamped)

±75

MODE INTERFACE (PIN MODE)

Logic Level for Positive Gain Slope

1.0

Logic Level for Negative Gain Slope

2.25

Input Resistance

200

kΩ

POWER SUPPLY (PIN VPS1, PIN VPS2,

PIN VPSV, PIN VPSL, PIN VPOS)

Supply Voltage

4.5

5.0

5.5

Quiescent Current per Channel

AD8331

AD8332, AD8334

Power Dissipation per channel

No signal

AD8331

125

AD8332, AD8334

145

Power-Down Current

AD8332 (VGA and LNA Disabled)

300

600

μA

AD8331 (VGA and LNA Disabled)

240

400

μA

LNA Current

AD8331 (ENBL)

Each channel

7.5

AD8332, AD8334 (ENBL)

Each channel

7.5

VGA Current

AD8331 (ENBV)

7.5

AD8332, AD8334 (ENBV)

7.5

PSRR

VGAIN = 0 V, f = 100 kHz

−68

1 All dBm values are referred to 50 Ω.

2 The absolute gain refers to the theoretical gain expression in Equation 1.

3 Best-fit to linear-in-dB curve.

4 The current is limited to ±1 mA typical.

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