AD7401 datasheet(4/20 Pages) AD

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AD7401

Rev. A | Page 4 of 20

Parameter

Y Version1, 2

Unit

Test Conditions/Comments

POWER REQUIREMENTS

VDD1

4.5/5.25

V min/V max

VDD2

3/5.5

V min/V max

IDD16

mA max

VDD1 = 5.25 V

IDD27

mA max

VDD2 = 5.5 V

mA max

VDD2 = 3.3 V

1 Temperature range is −40°C to +85°C.

2 All voltages are relative to their respective ground.

3 See the Terminology section.

4 For fMCLK > 16 MHz to 20 MHz, mark space ratio is 48/52 to 52/48, VDD1 = VDD2 = 5 V ± 5% and TA = −40°C to +85°C.

5 Sample tested during initial release to ensure compliance.

6 See Figure 15.

7 See Figure 17.

TIMING SPECIFICATIONS1

VDD1 = 4.5 V to 5.25 V, VDD2 = 3 V to 5.5 V, TA = TMAX to TMIN, unless otherwise noted.

Table 2.

Parameter

Limit at TMIN, TMAX

Unit

Description

fMCLKIN2,3

MHz max

Master clock input frequency

MHz min

Master clock input frequency

t14

ns max

Data access time after MCLK rising edge

t24

ns min

Data hold time after MCLK rising edge

0.4 × tMCLKIN

ns min

Master clock low time

0.4 × tMCLKIN

ns min

Master clock high time

1 Sample tested during initial release to ensure compliance.

2 Mark space ratio for clock input is 40/60 to 60/40 for fMCLKIN to 16 MHz and 48/52 to 52/48 for fMCLKIN > 16 MHz to 20 MHz.

3 VDD1 = VDD2 = 5 V

± 5% for fMCLKIN > 16 MHz to 20 MHz.

4 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.

200µA

IOL

200µA

IOH

1.6V

TO OUTPUT

25pF

Figure 2. Load Circuit for Digital Output Timing Specifications

MCLKIN

MDAT

Figure 3. Data Timing

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