AD1870

REV. A

–13–

Timing Parameters

For master modes, a BCLK transmitting edge (labeled “XMIT”)

in Figure 17. A L

RCK transition will be delayed from a BCLK

falling edge will be delayed from a BCLK transmitting edge by

For slave modes, an L

RCK transition must be set up to a BCLK

The DATA and TAG outputs will be delayed from an L

RCK

Mode, Data Position Controlled by WCLK Input, WCLK must

For both Master and Slave Modes, BCLK must have a mini-

The AD1870 CLKIN and

RESET timing is shown in Figure 19.

requirements for

RESET.

Master Clock (CLKIN) Considerations

It is recommended that the BCLK and L

RCK are derived from

CLKIN to ensure correct phase relationships. The modulator

of the AD1870 runs at 64

× f

obtained when the BCLK rate equals 64

rates such as 48

× f

floor, depending on the phase relationship of BCLK to CLKIN.

Synchronizing Multiple AD1870s

Multiple AD1870s can be synchronized by making all the

AD1870s serial port slaves. This option is illustrated in Figure 6.

See the Reset, Autocalibration, and Power-Down section for

additional information.

#1 AD1870

SLAVE MODE

CLKIN

DATA

BCLK

WCLK

L

RCK

CLOCK

SOURCE

#2 AD1870

SLAVE MODE

CLKIN

DATA

BCLK

WCLK

L

RCK

#N AD1870

SLAVE MODE

CLKIN

DATA

BCLK

WCLK

L

RCK

RESET

RESET

RESET

Figure 6. Synchronizing Multiple AD1870s