AD8367 datasheet(17/24 Pages) AD

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AD8367

Rev. A | Page 17 of 24

VOUT 10

DECL 9

OCOM 8

10nF

GAIN

DETO

ICOM

10k

AD8367

ICOM

ICOM 14

ENBL

HPFL 13

INPT

VPSI 12

MODE

VPSO 11

INPUT

10nF

57.6

CHP

10nF

RHP

100

VAGC

AD820

VSET

0.1

μF

82k

20pF

3.3nF

AD8361

PWDN

COMM

RFIN

FLTR

IREF

VRMS 7

VPOS

SREF

150k

33k

200k

10nF

0.1

μF

2.2

12k

0.27

μF

Vrms

VOUT INTO A

200

Ω LOAD

Figure 38. Example of Using an External Detector to Form an AGC Loop

Note that in this circuit the AD8367’s MODE pin must be

pulled high to obtain correct feedback polarity because the

integrator inverts the polarity of the feedback signal.

The relationship between the setpoint voltage and the rms

output voltage of the AD8367 is

(

)

7.5

225

−

SET

RMS

OUT

(6)

where 225 is the input resistance of the AD8361 and 7.5 is its

conversion gain. For R1 = 200 Ω, this reduces to VOUT –RMS = VSET

× 0.25.

Capacitor C2 sets the averaging time for the rms detector. This

should be made long enough to provide sufficient smoothing of

the detector’s output in the presence of the modulation on the

RF signal. A level fluctuation of less than 1 dB (<5% to 10%) p-p

at the AD8361’s output is a reasonable value. A considerably

longer time constant needlessly lowers the AGC bandwidth,

while a short time constant can degrade the accuracy of the

true-rms measurement process. Components C1, R2, and R3

set the control loop’s bandwidth and stability. The maximum

stable loop bandwidth is limited by the rms detector’s averaging

time constant as previously discussed.

For an input signal consisting of a 4.096 MS/s QPSK modulated

carrier, the relationship between VSET and the output power for

this setup is shown in Figure 39. The exponential shape reflects

the linear-in-magnitude response of the AD8361. The adjacent

channel power ratio (ACPR) as a function of output power is

illustrated in Figure 40. The minima occur where the distortion

and integrated noise powers cross over.

The component values shown in Figure 38 were chosen for a

64-QAM signal at 500 kS/s at a carrier frequency of 150 MHz.

The response time of the loop as shown is roughly 5 ms for

an abrupt input level change of 40 dB. Figure 41 shows the

dynamic performance of the loop with a step-modulated

CW signal applied to the input for a VSET of about 1 V.

For a linear-in-dB response, detectors such as the AD8318 or

the AD8362 can be used in place of the AD8361.

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

–20

–5

–10

–15

10MHz

380MHz

POUT (dBm INTO 200

Ω)

Figure 39. AGC Setpoint Voltage vs. Output Power

(QPSK: 4.096 MS/s; α = 0.22; 1 User)

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