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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AT89C5131A-RDTUL датащи(PDF) 16 Page - ATMEL Corporation |
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AT89C5131A-RDTUL датащи(HTML) 16 Page - ATMEL Corporation |
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16 / 185 page  16 AT89C5131A-L 4338E–USB–06/06 Registers Table 14. CKCON0 (S:8Fh) Clock Control Register 0 Reset Value = 0000 0000b 76 54 32 1 0 TWIX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2 Bit Number Bit Mnemonic Description 7TWIX2 TWI Clock This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit has no effect. Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 6WDX2 Watchdog Clock This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit has no effect. Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 5 PCAX2 Programmable Counter Array Clock This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit has no effect. Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 4SIX2 Enhanced UART Clock (Mode 0 and 2) This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit has no effect. Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 3T2X2 Timer2 Clock This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit has no effect. Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 2T1X2 Timer1 Clock This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit has no effect. Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 1T0X2 Timer0 Clock This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit has no effect. Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 0X2 System Clock Control bit Clear to select 12 clock periods per machine cycle (STD mode, FCPU = FPER = FOSC/2). Set to select 6 clock periods per machine cycle (X2 mode, F CPU = FPER = FOSC). |
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