WM9714LGEFLSLASHV datasheet(13/94 Pages) WOLFSON

13 / 94 page

Pre-Production

WM9714L

PP Rev 3.0 June 2006

CLOCK GENERATION

WM9714L supports clocking from 2 separate sources, which can be selected via the AC’97 interface:

•

External clock input MCLKA

•

External clock input MCLKB

The source clock is divided to appropriate frequencies in order to run the AC’97 interface, PCM

interface, voice DAC and Hi-fi DSP by means of a programmable divider block. Clock rates may be

changed during operation via the AC’97 link in order to support alternative modes, for example low

power mode when voice data is being transmitted only. A PLL is present to add flexibility in selection

of input clock frequencies, typical choices being 2.048MHz, 4.096MHz or 13MHz.

Default mode on power-up assumes a clock will be present on MCLKA with the PLL powered down.

This enables data to be clocked via the AC’97 link to define the desired clock divider mode and

whether PLL needs to be activated.

Note: This clock can be any available frequency.

When muxing between MCLKA and MCLKB both clocks must be active for at least two clock cycles

after the switching event.

CLOCK DIVISION MODES

Figure 2 shows the clocking strategy for WM9714L. Clocking is controlled by CLK_MUX, CLK_SRC

and S[6:0].

•

CLKAX2, CLKBX2 – clock doublers on inputs MCLKA and MCLKB.

•

CLK_MUX - selects between MCLKA and MCLKB.

•

CLK_SRC – selects between external or PLL derived clock reference.

•

S[3:0] – sets the voice DAC clock rate and PCM interface clock when in master mode

(division ratio 1 to 16 available).

•

S[6:4] - sets the hi-fi clocking rate (division ratio 1 to 8 available).

The registers used to set these switches can be accessed from register address 44h (see Table 2).

If a mode change requires switching from an external clock to a PLL generated clock then it is

recommended to set the clock division ratios required for the PLL clock scheme prior to switching

between clocks. This option is accommodated by means of two sets of registers. SPLL[6:0] is used to

set the divide ratio of the clock when in PLL mode and SEXT[6:0] is used to divide the clock when it is

derived from an external source. If the PLL is selected (CLK_SRC = 0), S[6:0] = SPLL[6:0]. SPLL[6:0]

is defined in register 46h (see Table 4) and is written to using the page address mode. More details

on page address mode for controlling the PLL are found on page 20. Register 46h also contains a

number of separate control bits relating to the PLL’s function. If an external clock is selected

(CLK_SRC = 1) S[6:0] = SEXT[6:0]. SEXT[6:0] is defined in register address 44h. Writing to registers

44h and 46h enables pre-programming of the required clock mode before the PLL output is selected.

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