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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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WM8976GEFL/V датащи(PDF) 67 Page - Wolfson Microelectronics plc |
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WM8976GEFL/V датащи(HTML) 67 Page - Wolfson Microelectronics plc |
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67 / 108 page  Pre-Production WM8976 w PP Rev 3.0 April 2006 67 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0 MS 0 Sets the chip to be master over LRC and BCLK 0=BCLK and LRC clock are inputs 1=BCLK and LRC clock are outputs generated by the WM8976 (MASTER) 4:2 BCLKDIV 000 Configures the BCLK output frequency, for use when the chip is master over BCLK. 000=divide by 1 (BCLK=SYSCLK) 001=divide by 2 (BCLK=SYSCLK) 010=divide by 4 011=divide by 8 100=divide by 16 101=divide by 32 110=reserved 111=reserved 7:5 MCLKDIV 010 Sets the scaling for either the MCLK or PLL clock output (under control of CLKSEL) 000=divide by 1 001=divide by 1.5 010=divide by 2 011=divide by 3 100=divide by 4 101=divide by 6 110=divide by 8 111=divide by 12 R6 Clock Generation Control 8 CLKSEL 1 Controls the source of the clock for all internal operation: 0=MCLK 1=PLL output Table 54 Clock Control |
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