WM8940GEFLSLASHV datasheet(64/85 Pages) WOLFSON

64 / 85 page

WM8940

Pre-Production

Pre-Production, Rev 3.0, February 2007

Disable DAC (DACEN = 0), speaker mixer (SPKMIX = 0), and speaker outputs (SPKPEN =

0 and SPKNEN = 0).

Reset all registers to their default state (software reset).

10.

Turn off external power supply voltages.

Notes:

This step enables the internal device bias buffer and the VMID buffer for unassigned

inputs/outputs. This will provide a startup reference for all inputs and outputs. This will

cause the inputs and outputs to ramp towards VMID in a way that is controlled and

predictable.

Choose the value of VMIDSEL bits based on the startup time (VMIDSEL = 10 for the

slowest startup, VMIDSEL = 11 for the fastest startup). Startup time is defined by the value

of the VMIDSEL bits (the reference impedance) and the external decoupling capacitor on

VMID.

In addition to the power on sequence, it is recommended that the zero cross functions are used

when changing the volume in the PGAs to avoid any audible pops and clicks.

POWER MANAGEMENT

VMID

The analogue circuitry will not work when VMID is disabled (VMIDSEL[1:0] = 00b). The impedance

of the VMID resistor string, together with the decoupling capacitor on the VMID pin will determine the

start-up time of the VMID circuit.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Power

management 1

1:0

VMIDSEL 00

Reference string impedance to VMID pin

(determines startup time):

00=off (open circuit)

01=75kΩ

10=300kΩ

11=2.5kΩ (for fastest startup)

Table 57 VMID Impedance Control

BIASEN

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Power

management 1

BIASEN

Analogue amplifier bias control

0=Disabled

1=Enabled

Table 58 BIASEN Control

ESTIMATED SUPPLY CURRENTS

When either the DAC or ADC are enabled it is estimated that approximately 4mA will be drawn from

DCVDD when fs=48kHz (This will be lower at lower sample rates). When the PLL is enabled an

additional 700 microamps will be drawn from DCVDD.

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