поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

Preview PDF HTML

WM8940 датащи(PDF) 13 Page - Wolfson Microelectronics plc

номер детали WM8940
подробное описание детали  Mono CODEC with Speaker Driver
PDF  85 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  WOLFSON [Wolfson Microelectronics plc]
домашняя страница  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8940 датащи(HTML) 13 Page - Wolfson Microelectronics plc

Back Button WM8940 Datasheet HTML 9Page - Wolfson Microelectronics plc WM8940 Datasheet HTML 10Page - Wolfson Microelectronics plc WM8940 Datasheet HTML 11Page - Wolfson Microelectronics plc WM8940 Datasheet HTML 12Page - Wolfson Microelectronics plc WM8940 Datasheet HTML 13Page - Wolfson Microelectronics plc WM8940 Datasheet HTML 14Page - Wolfson Microelectronics plc WM8940 Datasheet HTML 15Page - Wolfson Microelectronics plc WM8940 Datasheet HTML 16Page - Wolfson Microelectronics plc WM8940 Datasheet HTML 17Page - Wolfson Microelectronics plc Next Button
Zoom Inzoom in Zoom Outzoom out
 13 / 85 page
background image
Pre-Production
WM8940
w
Pre-Production, Rev 3.0, February 2007
13
Test Conditions
DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA=+25
oC, Slave Mode, fs=48kHz, MCLK=256fs,
24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
FRAME propagation delay from BCLK falling edge
tDL
10
ns
ADCDAT propagation delay from BCLK falling edge
tDDA
15
ns
DACDAT setup time to BCLK rising edge
tDST
10
ns
DACDAT hold time from BCLK rising edge
tDHT
10
ns
AUDIO INTERFACE TIMING – SLAVE MODE
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA=+25
oC, Slave Mode, fs=48kHz, MCLK= 256fs,
24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
81.38
ns
BCLK pulse width high
tBCH
32.55
ns
BCLK pulse width low
tBCL
32.55
ns
FRAME set-up time to BCLK rising edge
tLRSU
10
ns
FRAME hold time from BCLK rising edge
tLRH
10
ns
DACDAT hold time from BCLK rising edge
tDH
10
ns
DACDAT set-up time to BCLK rising edge
tDS
10
ns
ADCDAT propagation delay from BCLK falling edge
tDD
15
ns
Note:
BCLK period should always be greater than or equal to MCLK period.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com