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WM8775SEDS/R датащи(PDF) 18 Page - Wolfson Microelectronics plc

номер детали WM8775SEDS/R
подробное описание детали  24-bit, 96kHz ADC with 4 Channel I/P Multiplexer
PDF  39 Pages
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производитель  WOLFSON [Wolfson Microelectronics plc]
домашняя страница  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8775SEDS/R датащи(HTML) 18 Page - Wolfson Microelectronics plc

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WM8775
Production Data
w
PD Rev 4.1, June 2006
18
LEFT CHANNEL
RIGHT CHANNEL
ADCLRC
BCLK
DOUT
1/fs
n
3
2
1
n-2 n-1
LSB
MSB
n
3
2
1
n-2 n-1
LSB
MSB
Figure 14 Right Justified Mode Timing Diagram
I
2S MODE
In I
2S mode, the MSB of the ADC data is output on DOUT and changes on the first falling edge of
BCLK following an ADCLRC transition and may be sampled on the rising edge of BCLK. ADCLRC is
low during the left samples and high during the right samples.
LEFT CHANNEL
RIGHT CHANNEL
ADCLRC
BCLK
DOUT
1/fs
n
3
2
1
n-2 n-1
LSB
MSB
n
3
2
1
n-2 n-1
LSB
MSB
1 BCLK
1 BCLK
Figure 15 I
2S Mode Timing Diagram
DSP MODE
In DSP/PCM mode, the left channel MSB is available on either the 1
st (mode B) or 2nd (mode A)
rising edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data
immediately follows left channel data. Depending on word length, BCLK frequency and sample rate,
there may be unused BCLK cycles between the LSB of the right channel data and the next sample.
In device master mode, the LRC output will resemble the frame pulse shown in Figure 16 and Figure
17. In device slave mode, Figure 18 and Figure 19, it is possible to use any length of frame pulse
less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period
before the rising edge of the next frame pulse.



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