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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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WM8772 датащи(PDF) 26 Page - Wolfson Microelectronics plc |
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WM8772 датащи(HTML) 26 Page - Wolfson Microelectronics plc |
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26 / 73 page  WM8772EDS – 28 LEAD SSOP Production Data w PD Rev 4.2 October 2005 26 DSP MODE A In DSP mode A, the MSB of DAC channel 1 left data is sampled by the WM8772EDS on the second rising edge on BCLK following a LRC rising edge. DAC channel 1 right and DAC channels 2 and 3 data follow DAC channel 1 left data (Figure 26). Figure 26 DSP Mode Audio Interface - Mode A Slave, DAC DACLRC DACBCLK DIN1 Input Word Length (IWL) 1/fs CHANNEL 1 LEFT n 2 1 n-1 LSB MSB n 2 1 n-1 CHANNEL 1 RIGHT 2 1 CHANNEL 2 LEFT n n-1 CHANNEL 3 RIGHT NO VALID DATA 1 BCLK 1 BCLK Figure 27 DSP Mode Audio Interface - Mode A Master, DAC The MSB of the left channel ADC data is output on DOUT and changes on the first falling edge of BCLK following a low to high LRC transition and may be sampled on the rising edge of BCLK. The right channel ADC data is contiguous with the left channel data (Figure 26) Figure 28 DSP Mode Audio Interface - Mode A Slave, ADC |
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