WM8706

Production Data

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PD Rev 4.1 July 2005

20

In DSP modes, the LRCIN register bit is used to select between early and late modes:

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

011

Interface Control

1

LRP

0

DSP Format (DSP modes)

0 : Early DSP mode

1: Late DSP mode

Table 18 DSP Format Control

In DSP early mode, the first bit is sampled on the BCKIN rising edge following the one that

detects a low to high transition on LRCIN. In DSP late mode, the first bit is sampled on the

BCKIN edge, which detects a low to high transition on LRCIN. No BCKIN rising edges are

allowed between the data words. The word order is DIN left, DIN right.

ATTENUATOR CONTROL MODE

Setting the ATC register bit causes the left channel attenuation settings to be applied to both

left and right channel DACs from the next audio input sample. No update to the attenuation

registers is required for ATC to take effect.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

011

Interface Control

2

ATC

0

Attenuate Control Mode:

0 : Right channels use Right

attenuation

1:

Right Channels use Left

Attenuation

Table 19 Attenuation Control Select

OUTPUT PHASE REVERSAL

The REV register bit controls the phase of the output signal. Setting the REV bit causes the

phase of the output signal to be inverted.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

011

Interface Control

4

REV

0

Analogue Output Phase

0: Normal

1: Inverted

Table 20 Output Phase Control

BCKIN POLARITY

By default, LRCIN and DIN are sampled on the rising edge of BCKIN and should ideally change

on the falling edge. Data sources which change LRCIN and DIN on the rising edge of BCKIN

can be supported by setting the BCP register bit. Setting BCP to 1 inverts the polarity of BCKIN

to the inverse of that shown in Figure 4, Figure 5, Figure 6, Figure 7 and Figure 8.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

011

Interface Control

5

BCP

0

BCKIN Polarity

0 : normal BCKIN polarity

1: inverted BCKIN polarity

Table 21 BCKIN Polarity Control

DE-EMPHASIS SAMPLE RATE SELECTION

The SF[1:0] bits are used to select the de-emphasis rate.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION **

0011

Interface Control

7:6

SF[1:0]

00

De-Emphasis Sample Rate Selection

00 : De-Emphasis Off

01: 48kHz

10: 44.1kHz

11: 32kHz

Table 22 De-emphasis Control

Note:

** There is only one internal de-emphasis mode optimised for 44.1kHz. This is in contrast to

WM8716 which is individually optimised for each sample rate.