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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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WM8510GEDS/RV датащи(PDF) 49 Page - Wolfson Microelectronics plc |
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WM8510GEDS/RV датащи(HTML) 49 Page - Wolfson Microelectronics plc |
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49 / 81 page  Pre-Production WM8510 w PD Rev 4.1 December 2006 49 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 1 ADCLRSWAP 0 Controls whether ADC data appears in ‘right’ or ‘left’ phases of FRAME clock: 0=ADC data appear in ‘left’ phase of FRAME 1=ADC data appears in ‘right’ phase of FRAME 2 DACLRSWAP 0 Controls whether DAC data appears in ‘right’ or ‘left’ phases of FRAME clock: 0=DAC data appear in ‘left’ phase of FRAME 1=DAC data appears in ‘right’ phase of FRAME 4:3 FMT 10 Audio interface Data Format Select: 00=Right Justified 01=Left Justified 10=I 2S format 11= DSP/PCM mode 6:5 WL 10 Word length 00=16 bits 01=20 bits 10=24 bits 11=32 bits (see note) 7 FRAMEP 0 Frame clock polarity 0=normal 1=inverted R4 Audio interface control 8 BCP 0 BCLK polarity 0=normal 1=inverted Table 41 Audio Interface Control AUDIO INTERFACE CONTROL The register bits controlling audio format, word length and master / slave mode are summarised below. Each audio interface can be controlled individually. Register bit MS selects audio interface operation in master or slave mode. In Master mode BCLK, and FRAME are outputs. The frequency of BCLK and FRAME in master mode are controlled with BCLKDIV. These are divided down versions of master clock. This may result in short BCLK pulses at the end of a frame if there is a non-integer ratio of BCLKs to FRAME clocks. |
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