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SWITCHING CHARACTERISTICS

TMDS341A

SLLS702B – MAY 2006 – REVISED MARCH 2007

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

TMDS DIFFERENTIAL PINS (Y/Z)

Propagation delay time, low-to-high-level output

250

800

ps

Propagation delay time, high-to-low-level output

250

800

ps

Differential output signal rise time (20% - 80%)

75

240

ps

Differential output signal fall time (20% - 80%)

75

240

ps

7

50

ps

Intra-pair differential skew, see Figure 5

23

50

ps

100

ps

Part-to-part skew

200

ps

Peak-to-peak output jitter from Y/Z(1) residual jitter

See Figure 8, PRE = 0 V

15

30

ps

Am/Bm = 1.65 Gbps HDMI data pattern,

m = 2, 3, 4

Peak-to-peak output jitter from Y/Z(2:4) residual jitter

18

50

ps

A1/B1 = 165 MHz clock

Peak-to-peak output jitter from Y/Z(1) residual jitter

See Figure 8, PRE = 0 V

20

22

ps

Am/Bm = 2.25 Gbps HDMI data pattern,

m = 2, 3, 4

Peak-to-peak output jitter from Y/Z(2:4) residual jitter

38

78

ps

A1/B1 = 225 MHz clock

Am/Bm = 250 Mbps HDMI data pattern,

De-emphasis duration

ps

m = 2, 3, 4

A1/B1 = 25 MHz clock

Select to switch output

6

10

ns

Enable time

See Figure 6

6

10

ns

Disable time

6

10

ns

DDC I/O PINS (SCL, SCL_SINK, SDA, SDA_SINK)

Propagation delay from SCLn to SCL_SINK or SDAn to

0.4

2.5

ns

SDA_SINK or SDA_SINK to SDAn

CONTROL AND STATUS PINS (S, HPD_SINK, HPD)

Propagation delay (from HPD_SINK to the active port of HPD)

2

6.0

ns

Switch time (from port select to the latest valid status of HPD)

3

6.5

ns

(1)

All typical values are at 25

°C and with a 3.3-V supply.

(2)

inputs are tied together.

(3)

between channel 1 of two devices, when both devices operate with the same source, the same supply voltages, at the same

temperature, and have identical packages and test circuits.

(4)

The typical value is ensured by simulation.

9

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