Discontinued

Part

CAT24FC01

3

Doc No. 1073, Rev. G

© 2005 by Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

Write Cycle Limits

Symbol

Parameter

MinTyp

Max

Un

its

Write Cycle Time

5

ms

A.C. CHARACTERISTICS

Read & Write Cycle Limits

Symbol

Parameter

2.5 V - 5.5 V

MinMax

Un

its

Clock Frequency

0

400

kHz

Noise Suppression Time Constant at SCL, SDA Inputs

100

ns

SCL Low to SDA Data Out and ACK Out

900

ns

Time the Bus Must be Free Before a New Transmission

1300

ns

Can Start

Start Condition Hold Time

600

ns

Clock Low Period

1300

ns

Clock High Period

600

ns

Start Condition Setup Time

600

ns

(for a Repeated Start Condition)

Data In Hold Time

0

ns

Data In Setup Time

100

ns

SDA and SCL Rise Time

300

ns

SDA and SCL Fall Time

300

ns

Stop Condition Setup Time

600

ns

Data Out Hold Time

100

ns

Note:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

Symbol

Parameter

MinTyp

Max

Un

its

Power-up to Read Operation

1

ms

Power-up to Write Operation

1

ms

The write cycle time is the time from a valid stop

condition of a write sequence to the end of the internal

program/erase cycle. During the write cycle, the bus

interface circuits are disabled, SDA is allowed to remain

high, and the device does not respond to its slave

address.