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SP8715/IG/MPAC датащи(PDF) 4 Page - Zarlink Semiconductor Inc |
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SP8715/IG/MPAC датащи(HTML) 4 Page - Zarlink Semiconductor Inc |
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4 / 11 page ![]() 3 SP8715 Electrical Characteristics (Continued) Guaranteed over the following conditions (unless otherwise stated): VCC=+2.7V to +5.25V (with respect to VEE), Output load (pin 4) = 10pF, Tamb = -40°C to +85°C (note 2) Characteristic Units Conditions Output level (pin 4) 500 600 mV p-p Modulus set-up time, ts (notes 5,6,8) 20 ns RF input = 1GHz Modulus hold time, th (notes 6,8) 1 ns RF input = 1GHz Power down time, tpd (notes 7,8) 10 µs See Figure 9 Power down recovery time, tpu 6 µs See Figure 9 (notes 7,8) NOTES 2. All electrical testing is performed at +85 °C. 3. Typical values are measured at +25 °C and VCC = +5V. 4. Modulus Control and Ratio Select are high impedance inputs which can be driven directly by standard CMOS outputs. 5. Modulus control is latched at the end of the previous cycle. 6. See Figure 4. 7. See Figure 8. 8. These parameters are not tested but are guaranteee by design. 9. The ratio select pin is not intended to be switched dynamically. Value Min. Typ. Max. OPERATING NOTES The RF inputs are biased internally and are normally coupled to the signal source with suitable capaitors. The output stage has a novel design and is intended to drive a CMOS synthesiser input. External pull- down resistors or circuits are not required. The SP8715 is not suitable for driving TTL or similar devices. The device will operate down to DC frequencies for non-sinusoidal signals provided that the input slew rate is better than 100V/ µs. POWER DOWN (pin 7) is connected internally to a pull-down resistor. If the battery economy facility is not used, pin 7 should be either left unconnected or connected to VEE. |
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