LAN9217 datasheet(39/134 Pages) SMSC

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16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX

Datasheet

SMSC LAN9217

Revision 1.5 (07-18-06)

DATASHEET

3.11.3.2

Energy Detect Power-Down

This power-down mode is activated by setting the Phy register bit 17.13 to 1. Please refer to Section

5.5.8, "Mode Control/Status," on page 113 for additional information on this register. In this mode when

no energy is present on the line, the PHY is powered down, with the exception of the management

interface, the SQUELCH circuit and the ENERGYON logic. The ENERGYON logic is used to detect

the presence of valid energy from 100Base-TX, 10Base-T, or Auto-negotiation signals

In this mode, when the ENERGYON signal is low, the PHY is powered-down, and nothing is

transmitted. When energy is received - link pulses or packets - the ENERGYON signal goes high, and

the PHY powers-up. It automatically resets itself into the state it had prior to power-down, and asserts

the INT7.1 bit of the register defined in Section 5.5.11, "Interrupt Source Flag," on page 116. If the

ENERGYON interrupt is enabled, this event will cause an interrupt to the host. The first and possibly

the second packet to activate ENERGYON may be lost.

When 17.13 is low, energy detect power-down is disabled.

3.12

Detailed Reset Description

The LAN9217 has five reset sources:

Power-On Reset (POR)

Hardware Reset Input Pin (nRESET)

Soft Reset (SRST)

PHY Soft Reset via PMT_CTRL bit 10 (PHY_RST)

PHY Soft Reset via PHY Basic Control Register (PHY REG 0.15)

Table 3.10 shows the effect of the various reset sources on the LAN9217's circuitry.

Note 3.10 After any PHY reset, the application must wait until the “Link Status” bit in the PHY’s “Basic

Status Register” (PHY Reg. 1.2) is set before attempting to transmit or receive data.

Note 3.11 After a POR, nRESET or SRST, the LAN9217 will automatically check for the presence

of an external EEPROM. After any of these resets the application must verify that the EPC

Busy Bit (E2P_CMD, bit 31) is cleared before attempting to access the EEPROM, or

change the function of the GPO/GPIO signals, or before modifying the ADDRH or ADDRL

registers in the MAC.

Note 3.12 HBI - “Host Bus Interface”, NASR - Not affected by software reset

Table 3.10 PHY Reset Sources and Effected Circuitry

RESET

SOURCE

PLL

HBI

Note

3.12

NASR

REGISTERS

Note 3.12

MIL

MAC

PHY

Note 3.10

EEPROM MAC

ADDR.

RELOAD

Note 3.11

CONFIG.

STRAPS

LATCHED

POR

nRESET

SRST

PHY_RST

PHY REG 0.15

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