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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AT80C51RA2-3CSCL датащи(PDF) 13 Page - International Rectifier |
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AT80C51RA2-3CSCL датащи(HTML) 13 Page - International Rectifier |
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13 / 85 page  13 4188E–8051–08/06 AT/TS8xC51Rx2 Figure 5-1. Clock Generation Diagram Figure 5-2. Mode Switching Waveforms The X2 bit in the CKCON register (Table 5-2) allows to switch from 12 clock cycles per instruc- tion to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature (X2 mode). Note: In order to prevent any incorrect operation while operating in X2 mode, user must be aware that all peripherals using clock frequency as time reference (UART, timers, PCA...) will have their time ref- erence divided by two. For example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. UART with 4800 baud rate will have 9600 baud rate. Table 5-2. CKCON Register CKCON - Clock Control Register (8Fh) XTAL1 2 CKCON reg X2 state machine: 6 clock cycles. CPU control FOSC FXTAL 0 1 XTAL1:2 XTAL1:2 XTAL1 CPU clock X2 bit X2 Mode STD Mode STD Mode 76 543 210 --- --- - X2 Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is indeterminate. Do not set this bit. 6- Reserved The value read from this bit is indeterminate. Do not set this bit. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. |
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