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ST72F262G2B6 датащи(PDF) 26 Page - STMicroelectronics

номер детали ST72F262G2B6
подробное описание детали  8-BIT MCU WITH FLASH OR ROM MEMORY, ADC, TWO 16-BIT TIMERS, I2C, SPI, SCI INTERFACES
PDF  172 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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ST72F262G2B6 датащи(HTML) 26 Page - STMicroelectronics

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.3 Low Power Modes
6.4.3.1 Interrupts
The AVD interrupt event generates an interrupt if
the corresponding Enable Control Bit (AVDIE) is
set and the interrupt mask in the CC register is re-
set (RIM instruction).
Mode
Description
WAIT
No effect on SI. AVD interrupts cause the
device to exit from Wait mode.
HALT
The SICSR register is frozen.
Interrupt Event
Event
Flag
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
AVD event
AVDF
AVDIE
Yes
No



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