CS5322GDWR28 datasheet(16/21 Pages) ONSEMI

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CS5322

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where:

PwrstgZ + RS

CSA Gain 2.0

Multiply the converterZ by the output current step

size to calculate where the output voltage should

recover to within the first switching cycle after a

transient. If the ConverterZ is higher than the value

required to recover to where the adaptive positioning

is set the remainder of the recovery will be controlled

by the error amp compensation and will typically

recover in 10−20 μs.

DVR + DIOUT

ConverterZ

Make sure that ΔVR is less than the expected peak

transient for a good transient response.

5. Adjust L and RL or RS as required to meet the best

combination of transient response, steady state output

voltage ripple and pulse width jitter.

Current Limit

When the sum of the Current Sense amplifiers (VITOTAL)

exceeds the voltage on the ILIM pin the part will enter hiccup

mode. For inductive sensing the ILIM pin voltage should be

set based on the inductor resistance (or current sense

resistor) at max temperature and max current. To set the level

of the ILIM pin:

6. VI(LIM) + R IOUT(LIM) CS to ILIM Gain

where:

R is RL or RS;

IOUT(LIM) is the current limit threshold.

For the overcurrent to work properly the inductor

time constant (L/R) should be ≤ the Current sense RC.

If the RC is too fast, during step loads the current

waveform will appear larger than it is (typically for a

few hundred μs) and may trip the current limit at a

level lower than the DC limit.

Adaptive Positioning

7. To set the amount of voltage positioning below the

DAC setting at no load connect a resistor (RV(FB))

between the output voltage and the VFB pin. Choose

RV(FB) as;

RV(FB) + NL Position VFB Bias Current

See Figure 4 for VFB Bias Current.

8. To set the difference in output voltage between no

load and full load, connect a resistor (RV(DRP))

between the VDRP and VFB pins. RV(DRP) can be

calculated in two steps. First calculate the difference

between the VDRP and VFB pin at full load. (The VFB

voltage should be the same as the DAC voltage during

closed loop operation.) Then choose the RV(DRP) to

source enough current across RV(FB) for the desired

change in output voltage.

DVV(DRP) + IOUTFL

CS to VDRP Gain

where:

R = RL or RS for one phase;

IOUTFL is the full load output current.

RV(DRP) + DVDRP

RV(FB) DVOUT

Calculate Input Filter Capacitor Current Ripple

The procedure below assumes that phases do not overlap

and output inductor ripple current (P−P) is less than the

average output current of one phase.

9. Calculate Input Current

IIN +

VOUT

IOUT

(Efficiency

VIN)

10. Calculate Duty Cycle (per phase).

Duty Cycle +

VOUT

(Efficiency

VIN)

11. Calculate Apparent Duty Cycle.

Apparent Duty Cycle + Duty Cycle

#of Phases

12. Calculate Input Filter Capacitor Ripple Current. Use

the chart in Figure 16 to calculate the normalized

ripple current (KRMS) based on the reciprocal of

Apparent Duty Cycle. Then multiply the input current

by KRMS to obtain the Input Filter Capacitor Ripple

Current.

Ripple (RMS) + IIN

KRMS

4.00

3.50

3.00

2.50

2.00

1.50

1.00

0.50

0.00

1/ Apparent Duty Cycle

Figure 16. Normalized Input Filter Capacitor

Ripple Current

DESIGN EXAMPLE

Choose the component values for a 12 V to 1.6 V, 35 A

converter with lossless current sensing, adaptive positioning

and a 45 A current limit. The adaptive positioning is chosen

30 mV above the nominal VOUT at no load and 40 mV below

the no−load position with 35 A out. The peak output voltage

transient is 70 mV max during a 32 A step current.

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