CS5166 datasheet(14/25 Pages) ONSEMI

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CS5166

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Soft Start capacitor is charged to its upper 2.7 V threshold.

During

overload

condition

the

Soft

Start

charge/discharge current ratio sets the duty cycle for the

pulses (2.0 μA/60 μA = 3.3%), while actual duty cycle is half

that due to the extended off time mode (1.65%) when VFB

is less than 1.0 V. The Soft Start hiccup pulses last for a 3.0

ms period at the end of which the duty cycle repeats if a fault

is detected, otherwise normal operation resumes.

The protection scheme minimizes thermal stress to the

regulator components, input power supply, and PC board

traces, as the overcurrent condition persists. Upon removal

of the overload, the fault latch is cleared, allowing normal

operation to resume. The current limit trip point can be

adjusted through an external resistor, providing the user with

the current limit set−point flexibility.

Figure 19. Demonstration Board Hiccup Mode Short

Circuit Protection. Gate Pulses are Delivered While

the Soft Start Capacitor Charges, and Cease During

Discharge

M 25.0 ms

Trace 3− Soft Start Timing Capacitor (1.0 V/div.)

Trace 4− 5.0 V Supply Voltage (2.0 V/div.)

Trace 2− Inductor Switching Node (2.0 V/div.)

Figure 20. Demonstration Board Startup with

Regulator Output Shorted To Ground

M 50.0 μs

Trace 4− 5.0 V from PC Power Supply (2.0 V/div.)

Trace 2− Inductor Switching Node (2.0 V/div.)

Overvoltage Protection

Overvoltage protection (OVP) is provided as result of the

normal operation of the V2 control topology and requires no

additional external components. The control loop responds

to an overvoltage condition within 100 ns, causing the top

MOSFET to shut off, disconnecting the regulator from it’s

input voltage. The bottom MOSFET is then activated,

resulting in a “crowbar” action to clamp the output voltage

and prevent damage to the load (see Figures 21 and 22 ). The

regulator will remain in this state until the overvoltage

condition ceases or the input voltage is pulled low. The

bottom FET and board trace must be properly designed to

implement the OVP function. If a dedicated OVP output is

required, it can be implemented using the circuit in Figure

23. In this figure the OVP signal will go high (overvoltage

condition), if the output voltage (VCORE) exceeds 20% of

the voltage set by the particular DAC code and provided that

PWRGD is low. It is also required that the overvoltage

condition be present for at least the PWRGD delay time for

the OVP signal to be activated. The resistor values shown in

Figure 23 are for VDAC = +2.8 V (DAC = 10111). The VOVP

(overvoltage trip−point) can be set using the following

equation:

VOVP + VBEQ3 1 ) R2

Figure 21. OVP Response to an Input−to−Output

Short Circuit by Immediately Providing 0% Duty

Cycle, Crow−Barring the Input Voltage to Ground

M 10.0 μs

Trace 1− Regulator Output Voltage (1.0 V/div.)

Trace 2− Inductor Switching Node 5.0 V/div.)

Trace 4− 5.0 V from PC Power Supply (5.0 V/div.)

Figure 22. OVP Response to an Input−to−Output Short

Circuit by Pulling the Input Voltage to Ground

M 5.00 ms

Trace 1− Regulator Output Voltage (1.0 V/div.)

Trace 4− 5.0 V from PC Power Supply (2.0 V/div.)

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