CS5156

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11

(see Figure 14). This circuit operates by pulling the Soft

circuit condition.

Figure 14. Implementing Shutdown with the CS5156

Shutdown

Input

5.0 V

MMUN2111T1 (SOT−23)

5

8 V

FFB

SS

IN4148

CS5156

External Power Good Circuit

An optional Power Good signal can be generated through

the use of four additional external components (see Figure

15). The threshold voltage of the Power Good signal can be

adjusted per the following equation:

VPower Good +

(R1 ) R2)

0.65 V

R2

This circuit provides an open collector output that drives

the Power Good output to ground for regulator voltages less

Figure 15. Implementing Power Good with the CS5156

5.0 V

Power Good

10 k

PN3904

6.2 k

R1

R2

PN3904

10 k

R3

CS5156

Figure 16. CS5156 Demonstration Board During Power

Up. Power Good Signal is Activated when Output

Voltage Reaches 1.70 V.

M 2.50 ms

Trace 4− 5.0 V Input (2.0 V/div.)

Trace 1− Regulator Output Voltage (1.0 V/div.)

Trace 2− Power Good Signal (2.0 V/div.)

Selecting External Components

The CS5156 can be used with a wide range of external

power components to optimize the cost and performance of

a particular design. The following information can be used

as general guidelines to assist in their selection.

NFET Power Transistors

Both logic level and standard MOSFETs can be used. The

reference designs derive gate drive from the 12 V supply

which is generally available in most computer systems and

use logic level MOSFETs. A charge pump may be easily

implemented to support 5.0 V only systems. Multiple

MOSFETs may be paralleled to reduce losses and improve

efficiency and thermal management.

Voltage applied to the MOSFET gates depends on the

application circuit used. The gate driver output is specified

to drive to within 1.5 V of ground when in the low state and

to within 2.0 V of its bias supply when in the high state. In

practice, the MOSFET gates will be driven rail to rail due to

overshoot caused by the capacitive load they present to the

output current, the following gate drive is provided;

VGATE(H) + 12 V * 5.0 V + 7.0 V

(see Figure 17.)