USB 2.0 Flash Media Controller

Datasheet

SMSC USB97C210

Page 13

Revision 1.5 (11-05-03)

DATASHEET

Chapter 5 Pin Descriptions

This section provides a detailed description of each signal. The signals are arranged in functional groups

according to their associated interface.

The “n” symbol in the signal name indicates that the active, or asserted state occurs when the signal is at a

low voltage level. When “n” is not present before the signal name, the signal is asserted when at the high

voltage level.

The terms assertion and negation are used exclusively. This is done to avoid confusion when working with

a mixture of “active low” and “active high” signal. The term assert, or assertion indicates that a signal is

active, independent of whether that level is represented by a high or low voltage. The term negate, or

negation indicates that a signal is inactive.

Table 5.1 - Pin Descriptions

NAME

SYMBOL

BUFFER

TYPE

DESCRIPTION

CompactFlash (In True IDE mode) Interface

CF Chip Select 1

CF_nCS1

O8

This pin is the active low chip select 1 signal for the CF

ATA device

CF Chip Select 0

CF_nCS0

O8

This pin is the active low chip select 0 signal for the task

file registers of CF ATA device in the True IDE mode.

CF Register Address 2

CF_SA2

O8

This pin is the register select address bit 2 for the CF

ATA device.

CF Register Address 1

CF_SA1

O8

Address signal 1 for the task file registers, when the

CFC is enabled in True IDE mode

CF Register Address 0

CF_SA0

O8

Address signal 0 for the task file registers, when the CFC

is enabled in True IDE mode.

CF Interrupt

CF_IRQ

IPD

This is the active high interrupt request signal from the

CF device.

This pin has an internal weak pull-down resistor.

CF

Data 15-8

CF_D[15:8]

IO8

The bi-directional data signals CF_D15-CF_D8 in True

IDE mode data transfer, when the CFC is enabled.

In the True IDE Mode, all of task file register operation

occur on the CF_D[7:0], while the data transfer is on

CF_D[15:0].

These pins have an internal weak pull-down resistor.

CF

Data7-0

CF_D[7:0]

IO8

The bi-directional data signals CF_D7-CF_D0 in the True

IDE mode data transfer.

In the True IDE Mode, all of task file register operation

occur on the CF_D[7:0], while the data transfer is on

CF_D[15:0].

These pins have an internal weak pull-down resistor.

IO Ready

CF_IORDY

IPU

This pin is active high input signal with an internal weak

pull-up resistor.