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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST72F324J2T3 датащи(PDF) 136 Page - STMicroelectronics |
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ST72F324J2T3 датащи(HTML) 136 Page - STMicroelectronics |
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136 / 163 page  ST72324 136/163 12.10 CONTROL PIN CHARACTERISTICS 12.10.1 Asynchronous RESET Pin Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Notes: 1. Data based on characterization results, not tested in production. 2. Hysteresis voltage between Schmitt trigger switching levels. 3. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on the RESET pin with a duration below th(RSTL)in can be ignored. 5. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy en- vironments. 6. Data guaranteed by design, not tested in production. Symbol Parameter Conditions Min Typ Max Unit Vhys Schmitt trigger voltage hysteresis 2) 2.5 V VIL Input low level voltage 1) 0.16xVDD V VIH Input high level voltage 1) 0.85xVDD VOL Output low level voltage 3) VDD=5V IIO=+2mA 0.2 0.5 V IIO Driving current on RESET pin 2 mA RON Weak pull-up equivalent resistor VDD=5V 20 30 120 k Ω tw(RSTL)out Generated reset pulse duration Internal reset sources 20 30 426) µs th(RSTL)in External reset pulse hold time 4) 2.5 µs tg(RSTL)in Filtered glitch duration 5) 200 ns 1 |
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