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ST72F324J2T3 датащи(PDF) 79 Page - STMicroelectronics

номер детали ST72F324J2T3
подробное описание детали  5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
PDF  163 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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ST72F324J2T3 датащи(HTML) 79 Page - STMicroelectronics

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10.4 SERIAL PERIPHERAL INTERFACE (SPI)
10.4.1 Introduction
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves however the SPI
interface can not be a master in a multi-master
system.
10.4.2 Main Features
Full duplex synchronous transfers (on 3 lines)
Simplex synchronous transfers (on 2 lines)
Master or slave operation
Six master mode frequencies (fCPU/4 max.)
fCPU/2 max. slave mode frequency (see note)
SS Management by software or hardware
Programmable clock polarity and phase
End of transfer interrupt flag
Write collision, Master Mode Fault and Overrun
flags
Note: In slave mode, continuous transmission is
not possible at maximum frequency due to the
software overhead for clearing status flags and to
initiate the next transmission sequence.
10.4.3 General Description
Figure 46 shows the serial peripheral interface
(SPI) block diagram. There are 3 registers:
– SPI Control Register (SPICR)
– SPI Control/Status Register (SPICSR)
– SPI Data Register (SPIDR)
The SPI is connected to external devices through
4 pins:
– MISO: Master In / Slave Out data
– MOSI: Master Out / Slave In data
– SCK: Serial Clock out by SPI masters and in-
put by SPI slaves
Figure 46. Serial Peripheral Interface Block Diagram
SPIDR
Read Buffer
8-Bit Shift Register
Write
Read
Data/Address Bus
SPI
SPIE
SPE
MSTR
CPHA
SPR0
SPR1
CPOL
SERIAL CLOCK
GENERATOR
MOSI
MISO
SS
SCK
CONTROL
STATE
SPICR
SPICSR
Interrupt
request
MASTER
CONTROL
SPR2
0
7
0
7
SPIF WCOL
MODF
0
OVR
SSI
SSM
SOD
SOD
bit
SS
1
0
1



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