ST662A

6/13

APPLICATION CIRCUIT

switches. This implies a critical layout design due to the need to minimize inductive paths and place

capacitors as close as possible to the device.

A good layout design is strongly recommended for noise reason. For best performance, use very short

connections to the capacitors and the values shown in table 1.

C3 and C4 must have low ESR in order to minimize the output ripple. Their values can be reduced to 2µF

and 1µF, respectively, when using ceramic capacitors, but must be of 10µF or larger if aluminium

electrolytic are chosen.

C5 must be placed as close to the device as possible and could be omitted if very low output noise

performance are not required.

Fig 13 and Fig 14 show, respectively, our EVALUATION kit layout and the relatively.

Figure 13 : KIT Lay-out

Figure 14 : Electrical Schematic