LM5145 datasheet(40/60 Pages) TI1

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9.2.2 Design 2 – High Density, 12-V, 8-A Rail From 48-V Telecom Power

Figure 9-16 shows the schematic diagram of a 400-kHz, 12-V output, 8-A synchronous buck regulator intended

for 48-V telecom applications.

BST

PGND

SS/TRK

COMP

AGND

VIN = 14 V to 85 V

VOUT = 12 V

LV5144

VOUT

SYNC In

GND

SYNCOUT

SYNCIN

EN/UVLO

VIN

ILIM

PGOOD

SYNC Out

VCC

COUT

CIN

RILIM

CVCC

CBST

CSS

RFB2

RFB1

RC2

CC2

CC1

RC1

CC3

RRT

CILIM

6.8 H

0.1 F

10 pF

47 nF

5 ´ 2.2 F

RUV2

9.31 kΩ

4.7 nF

5 ´ 22 μF

RUV1

100 kΩ

2.2 μF

CVIN

619 Ω

0.1 μF

1.5 kΩ

21 kΩ

100 pF

8.06 kΩ

100 Ω

24.9 kΩ

1 nF

RBST

2.2 Ω

optional

PGOOD

RVIN

2.2 Ω

Figure 9-16. Application Circuit 2 With LV5144 48-V to 12-A Synchronous Buck Regulator at 400 kHz

9.2.2.1 Design Requirements

The required input, output, and performance parameters for this application example are shown in Table 9-7.

Table 9-7. Design Parameters

DESIGN PARAMETER

VALUE

Input voltage range (steady state)

14 V to 85 V

Input transient voltage (peak)

90 V

Output voltage and current

12 V, 8 A

Input UVLO thresholds

14 V on, 13 V off

Switching frequency

400 kHz

Output voltage regulation

±1%

Load transient peak voltage deviation, 4-A load step

< 120 mV

9.2.2.2 Detailed Design Procedure

A high power density, high-efficiency regulator design uses 100-V power MOSFETs in SON 5-mm × 6-mm

packages, together with a low-DCR inductor and all-ceramic capacitor design. The design occupies a footprint of

30 mm × 15 mm on a single-sided PCB. The overcurrent (OC) setpoint in this design is set at 12 A based on the

resistor RILIM and the 10-mΩ RDS(on) of the low-side MOSFET (typical at TJ = 25°C and VGS = 10 V). The 12-V

output is connected to VCC through a diode, D1, to reduce IC bias power dissipation at high input voltages.

LV5144

SNVSCJ1 – AUGUST 2023

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