8.3 Power Supply Recommendations

The LOG200 has a maximum supply voltage of 12.6 V (±6.3 V) and a minimum supply voltage of 4.5 V

(±2.25 V). Decoupling capacitors must be used on the power supply and VCM pins.

In many cases, a 5

‑V single-ended supply or ±5‑V bipolar supply is used. If the only power supply available in

the system is a 3.3

‑V single-ended supply, a boost converter is needed to achieve the 4.5‑V minimum operating

voltage required by the LOG200. This approach can require larger decoupling capacitors to reduce the effects of

power-supply ripple on the device.

8.4 Layout

8.4.1 Layout Guidelines

Attention to good layout practices is always recommended. For best operational performance of the device, use

good printed circuit board (PCB) layout practices, including:

• Make sure that both input paths of the secondary amplifier are symmetrical and well-matched for source

impedance and capacitance to avoid converting common-mode signals into differential signals and thermal

electromotive forces (EMFs).

• Noise can propagate into analog circuitry through the power pins of the device and of the circuit as a whole.

Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the analog

circuitry. Connect low-ESR, 0.1-µF X7R ceramic bypass capacitors between each supply pin and ground,

placed as close as possible to the device. A single bypass capacitor from V+ to ground is applicable for

single-supply applications.

• Use a C0G (NP0) ceramic capacitor for the VCM decoupling capacitance and place as close to the VCM pin

as possible.

• Connect C0G (NP0) ceramic bypass capacitors to each of the REF165 and REF25 reference pins, as close

to the pins as possible. Use a sum of 250 pF to 350 pF of capacitance per pin.

• For photoelectric-sensing applications, place the photodiode as close as possible to the I1 pin to minimize

parasitic inductance.

• Use ceramic C0G (NP0)-dielectric capacitors for any capacitance that is part of the input or output signal

chain (C3, C4, C5, and CBIAS if implemented).

• Surround the current input traces with copper guard traces all the way from the source to the input pins of the

LOG200. Remove all solder mask and silkscreen from the guard area to reduce surface-charge accumulation

and prevent surface-level leakage paths. Use VCM as the guard potential.

– For ultra-low current measurements, the guard must be implemented in a three-dimensional scheme to

prevent leakage currents originating in other layers from flowing into the signal path. Place additional

guard copper on the next layer directly below the surface-level signal and guard traces to protect from

vertical leakage paths. Surround the sensitive input traces with a via fence connecting the guard copper

on different layers to complete the three-dimensional guard enclosure.

• To reduce parasitic coupling, run the input traces as far away as possible from the supply or output traces.

If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than in

parallel with the noisy trace.

• Minimize the number of thermal junctions. Ideally, the signal path is routed within a single layer without vias,

with the traces as short as possible.

• Keep sufficient distance from major thermal energy sources (circuits with high power dissipation). If not

possible, place the device so that the effects of the thermal energy source on the high and low sides of the

differential signal path are evenly matched.

• Solder the thermal pad to the PCB. For the LOG200 to properly dissipate heat and minimize leakage,

connect the thermal pad to a plane or large copper pour that is electrically connected to VCM, even for

low-power applications.

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LOG200

SBOSA28 – AUGUST 2023

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