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TAS5518 датащи(PDF) 16 Page - Texas Instruments

номер детали TAS5518
подробное описание детали  8 Channel Digital Audio PWM Processor
PDF  103 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
Logo TI - Texas Instruments

TAS5518 датащи(HTML) 16 Page - Texas Instruments

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Introduction
7
SLES115 — August 2004
TAS5518
TERMINAL
DESCRIPTION
TERMIN-
ATION
5-V
TOLERANT
I/O
NO.
DESCRIPTION
TERMIN-
ATION
5-V
TOLERANT
I/O
NAME
28
SDIN4
DI
5 V
Pulldown Serial audio data 4 input is one of the serial data input ports. SDIN4 supports four
discrete (stereo) data formats and is capable of inputting data at 64 Fs.
29
SDIN3
DI
5 V
Pulldown Serial audio data 3 input is one of the serial data input ports. SDIN3 supports four
discrete (stereo) data formats and is capable of inputting data at 64 Fs.
30
SDIN2
DI
5 V
Pulldown Serial audio data 2 input is one of the serial data input ports. SDIN2 supports four
discrete (stereo) data formats and is capable of inputting data at 64 Fs.
31
SDIN1
DI
5 V
Pulldown Serial audio data 1 input is one of the serial data input ports. SDIN1 supports four
discrete (stereo) data formats and is capable of inputting data at 64 Fs.
32
PSVC
O
Power supply volume control PWM output
33
VR_DIG
P
Voltage reference for digital core supply 1.8 V. A pin-out of the internally regulated
1.8-V power used by digital core logic. A 0.47-µF low ESR capacitor should be
connected between this terminal and DVSS. This terminal must not be used to
power external devices
34
DVSS
P
Digital ground
35
DVSS
P
Digital ground
36
DVDD
P
3.3-V digital power supply
37
BKND_ERR
DI
Pull up
Active low. A backend error sequence is generated by applying logic low to this
terminal. The BKND_ERR results in all system parameters unaffected, while all
H-bridge drive signals going to a hard mute (M) state.
38
DVSS
P
Digital ground
39
VALID
DO
Output indicating validity of PWM outputs active high
40
PWM_M_1
DO
PWM 1 output (differential −)
41
PWM_P_1
DO
PWM 1 output (differential +)
42
PWM_M_2
DO
PWM 2 output (differential −)
43
PWM_P_2
DO
PWM 2 output (differential +)
44
PWM_M_3
DO
PWM 3 output (differential −)
45
PWM_P_3
DO
PWM 3 output (differential +)
46
PWM_M_4
DO
PWM 4 output (differential −)
47
PWM_P_4
DO
PWM 4 output (differential +)
48
VR_PWM
P
Voltage reference for digital PWM core supply 1.8 V. A pin-out of the internally
regulated 1.8-V power used by digital PWM core logic. A 0.1-µF low ESR capacitor
should be connected between this terminal and DVSS_PWM. This terminal must
not be used to power external devices.
49
PWM_M_7
DO
PWM 7 (Line out L) output (differential −)
50
PWM_P_7
DO
PWM 7 (Line out L) output (differential +)
51
PWM_M_8
DO
PWM 8 (Line out R) output (differential −)
52
PWM_P_8
DO
PWM 8 (Line out R) output (differential +)
53
DVSS_PWM
P
Digital ground for PWM
54
DVDD_PWM
P
3.3-V digital power supply for PWM
55
PWM_M_5
DO
PWM 5 output (differential −)
56
PWM_P_5
DO
PWM 5 output (differential +)
57
PWM_M_6
DO
PWM 6 output (differential −)
58
PWM_P_6
DO
PWM 6 output (differential +)
59
PWM_HPML
DO
PWM left channel headphone (differential −)
60
PWM_HPPL
DO
PWM left channel headphone (differential +)
61
PWM_HPMR
DO
PWM right channel headphone (differential −)
62
PWM_HPPR
DO
PWM right channel headphone (differential +)



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