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RT6203ENGSP датащи(PDF) 19 Page - Richtek Technology Corporation |
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RT6203ENGSP датащи(HTML) 19 Page - Richtek Technology Corporation |
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19 / 21 page ![]() RT6203E 19 DS6203E-00 January 2019 www.richtek.com © Copyright 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Figure 7. PCB Layout Guide The feedback trace is on bottom layer and shielded by GND plane of inner layer. Input capacitors must be placed as close to IC VIN-GND as possible GND 2 3 4 5 6 7 8 9 EN SDA SCL SW should be connected to inductor by wide and short trace. Keep sensitive components away from this trace . Keep analog components away from the BOOT nodes. Add 12 thermal vias with 0.25mm diameter on exposed pad for thermal dissipation and current carrying capacity. Suggest inner layers are GND plane. Extend the GND plane for better thermal dissipation. Keep digital signal away from the noise traces and shielded by GND plane. Four-layer or six-layer PCB with maximum ground plane is strongly recommended for good thermal performance. CVCC CIN1 CIN2 CIN3 CBOOT COUT1 COUT2 COUT3 COUT4 COUT5 L |
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