RT3662EB datasheet(23/28 Pages) RICHTEK

23 / 28 page

RT3662EB

is a registered trademark of Richtek Technology Corporation.

DS3662EB-04

August

2019

www.richtek.com

Thermal Indicator

Refer to Figure 6, the RT3662EB provides the thermal

indicator. The VRHOT_L pin is an open-drain output

which is used for VR thermal indicator. When the

sensed voltage at TSEN pin is less than 2.2V, the

VRHOT_L signal will be pulled low to notify GPU that

the temperature is over the VRHOT temperature

threshold.

After TSEN pin setting, a 80

A current (when VCC = 5V)

will be generated at the TSEN pin for thermal indicator

function. And the voltage at TSEN pin as below :

NTC

TSEN

NTC

80 A

VREF

























 





 



(4)

Due to the VREF reference voltage cause the thermal

compensation become complex. In this way, the sensed

voltage related VREF will be eliminated in ADC block.

The actual sensed voltage at TSEN pin described as

below :

NTC

TSEN_ADC

NTC

80 A























 





 



(5)

TSEN

VREF

Rp1

Rp2

80µA

(VCC = 5V)

ADC

VTSEN_DIV

PHOCP

FSW

Initial

Offset

RNTC

VTSEN

Thermal

Monitor

VDDIO

PROCHOT_L

VRHOT_L

2.2V

Figure 6. TSEN Circuit

VDDC Controller

Active Phase Determination

The number of active phases is determined by the

internal circuitry that monitors the ISEN2N voltage

during start-up. Normally, the VDDC controller operates

as a 2-phase PWM controller. Pulling ISEN2N to VCC

programs a 1-phase operation. At EN rising edge,

VDDC controller detects whether the voltage of ISEN2N

is higher than “VCC

 0.5V” to decide how many

phases should be active and the active phase number is

determined and latched. The unused ISEN2P pin is

recommended to be connected to VCC.

Loop Control

The VDDC controller adopts Richtek's proprietary

G-NAVPTM topology. The G-NAVPTM is based on the

finite gain peak current mode with CCRCOT (Constant

Current Ripple Constant On-Time) topology. The output

voltage, VVDDC will decrease with increasing output load

current. The control loop consists of PWM modulators

with power stages, current sense amplifiers and an error

amplifier as shown in Figure 7.

Similar to the peak current mode control with finite

compensator gain, the HS_FET on-time is determined

by CCRCOT on-time generator. When load current

increases (VCS increases), the steady state COMP

voltage also increases and induces VVDDC_SENSE to

decrease, thus achieving AVP. A near-DC offset

canceling is added to the output of EA to eliminate the

inherent output offset of finite gain peak current mode

controller.

VVDDC

VVDDC_SENSE

ISENxP

ISENxN

1.867m

VCS

VIN

RGND

COMP

HS_FET

LS_FET

RX1

VSS_SENSE

VDAC

CCRCOT

PWM

Logic

Offset

Canceling

IMON

VREF_PINSET

RIMON

RSENSE

Driver

RX2

0.75 x AI_VDDC

Figure 7.VDDC Controller : Simplified Schematic with

Voltage Loop and Current Loop

Current Signal Sensing

Refer to Figure 7, for different RSENSE resistor, the

current sense method can classify as two types. The

method1 only use Rx1 for lower RSENSE application, and

the method2 use Rx1 and Rx2 to divide the current

signal for higher RSENSE application. Richtek also

provide Excel based design tool to let user choose the

appropriate components quickly.

The current sense topology of the VDDC controller is

continuous inductor current sensing. Therefore, the

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