RT1025WS datasheet(13/24 Pages) RICHTEK

13 / 24 page

RT1025

is a registered trademark of Richtek Technology Corporation

DS1025-01

July

2022

www.richtek.com

Read Function

■ Reading One Indexed Byte of Data from RT (With 1-Byte)

■ Reading n Indexed Words of Data from RT (With N-Byte)

Write Function

■ Writing One Indexed Byte of Data to RT (With 1-Byte)

■ Writing n Indexed Words of Data to RT (With N-Byte)

Slave Address

Data Byte

Acknowledge from RT

R/W

(n-1)th Byte

nth Byte

Data Byte

1st Byte

Acknowledge from RT

Data Byte

2nd Byte

…

Slave Address

Data Byte

R/W

Acknowledge from RT

1Byte

Slave Address

Data Byte

Acknowledge from RT

Acknowledge from Master

Slave Address

Acknowledge from RT

Repeated Start

Data Byte

Acknowledge from Master

……

R/W

1st Byte

2nd Byte

(n-1)th Byte

nth Byte

Slave Address

Data Byte

R/W

Acknowledge from RT

Acknowledge from Master

Slave Address

Acknowledge from RT

Repeated Start

R/W

1Byte

SPI Interface

The general protocol for the SPI interface is shown in

the figures below. The falling edge of CSN initiates the

start of the SPI bus cycle. The first byte of the

transaction is the command/address byte. When the

SPI master is writing data, data may change when the

clock is low, and must be stable on the clock rising

edge. Similarly, output data written to the SPI master is

shifted out on the falling edge of clock and can be

latched by the master on the rising edge of the clock.

The SPI slave controller data format is LSBF (least

significant bit first). The setup/hold/idle time should be

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