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WM8971L датащи(PDF) 40 Page - Wolfson Microelectronics plc |
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WM8971L датащи(HTML) 40 Page - Wolfson Microelectronics plc |
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40 / 61 page ![]() WM8971L Production Data w PD Rev 4.1 August 2005 40 In DSP/PCM mode, the left channel MSB is available on either the 1 st (mode B) or 2nd (mode A) rising edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample. In device master mode, the LRC output will resemble the frame pulse shown in Figure 22 and Figure 23. In device slave mode, Figure 24 and Figure 25, it is possible to use any length of frame pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period before the rising edge of the next frame pulse. Figure 22 DSP/PCM Mode Audio Interface (mode A, LRP=0, Master) Figure 23 DSP/PCM Mode Audio Interface (mode B, LRP=1, Master) Figure 24 DSP/PCM Mode Audio Interface (mode A, LRP=0, Slave) |
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