UPD703003A datasheet(28/45 Pages) RENESAS

28 / 45 page

µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)

Data Sheet U13188EJ6V1DS

(6) Write timing (1/2)

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

Delay time from CLKOUT

↑ to address <20> tDKA

Delay time from CLKOUT

↑ to R/W, UBEN, LBEN <78> tDKA2

–2

+13

Delay time from CLKOUT

↓ to ASTB <22> tDKST

Delay time from CLKOUT

↑ to DSTB <23> tDKD

WAIT setup time (to CLKOUT

↓) <26> tSWTK

WAIT hold time (from CLKOUT

↓) <27> tHKWT

Address hold time (from CLKOUT

↑) <28> tHKA

Address setup time (to ASTB

↓) <29> tSAST

–40

°C ≤ TA ≤ +70°C

0.5T – 10

°C < TA ≤ 85°C

0.5T – 12

Address hold time (from ASTB

↓) <30> tHSTA

0.5T – 10

Delay time from ASTB

↓ to DSTB↓ <34> tDSTD

0.5T – 10

Delay time from DSTB

↓ to ASTB↓ <37> tDDSTH

0.5T – 10

DSTB low-level width

<39> tWDL

–40

°C ≤ TA ≤ +70°C

(1 + n)T – 10

°C < TA ≤ 85°C

(1 + n)T – 13

ASTB high-level width

<40> tWSTH

T – 10

WAIT setup time (to address)

<41> tSAWT1

≥ 1, –40°C ≤ TA ≤ +70°C

1.5T – 20

≥ 1, 70°C < TA ≤ 85°C

1.5T – 24

<42> tSAWT2

≥ 1, –40°C ≤ TA ≤ +70°C

(1.5 + n)T – 20

≥ 1, 70°C < TA ≤ 85°C

(1.5 + n)T – 24

WAIT hold time (from address)

<43> tHAWT1

≥ 1

(0.5 + n)T

<44> tHAWT2

≥ 1

(1.5 + n)T

WAIT setup time (to ASTB

↓)

<45> tSSTWT1

≥ 1, –40°C ≤ TA ≤ +70°C

T – 18

≥ 1, 70°C < TA ≤ 85°C

T – 20

<46> tSSTWT2

≥ 1

(1 + n)T – 15

WAIT hold time (from ASTB

↓)

<47> tHSTWT1

≥ 1

<48> tHSTWT2

≥ 1

(1 + n)T

Address hold time (from CLKOUT

↑) <49> tDKOD

–40

°C ≤ TA ≤ +70°C

°C < TA ≤ 85°C

Delay time from DSTB

↓ to data output <50> tDDOD

Data output hold time (from CLKOUT

↑) <51> tHKOD

Data output setup time (to DSTB

↑) <52> tSODD

(1 + n)T – 15

Data output hold time (from DSTB

↑) <53> tHDOD

T – 10

Remarks 1. T = tCYK

2. n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may

vary when using the programmable wait insertion function.

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