TAS5036AIPFCRG4 datasheet(22/62 Pages) TI

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Architecture Overview

SLES061B—November 2002—Revised January 2004

TAS5036A

Table 2−6. Device Outputs During Reset

SIGNAL

MODE

SIGNAL STATE

Valid 1−Valid 6

All

Low

PWM_P outputs

All

Low

PWM_M outputs

All

Low

MCLK_OUT

All

Low

SCLK

Master

Low

SCLK

Slave

Signal input

LRCLK

Master

Low

LRCLK

Slave

Signal input

SDA

All

Signal input

CLIP

All

High

Because the RESET is an asynchronous control signal, small clicks and pops can be produced during the

application (the leading edge) of this control. However, when RESET is released, the transition from the hard

mute state back to normal operation is performed synchronously using a quiet sequence.

If a completely quiet reset sequence is desired, MUTE should be applied before applying RESET.

Table 2−7. Values Set During Reset

CONTROL

SETTING

Volume

0 dB

MCLK_IN frequency

256

Master/slave mode

M_S terminal state

Automute

Enabled

De-emphasis

None

DC offset

Interchannel delay

Each channel is set to default value

2.2.2 Power Down—PDN

The TAS5036A can be placed into the power-down mode by holding the PDN terminal low. When the

power-down mode is entered, both the PLL and the oscillator are shut down. Volume is immediately set to full

attenuation (there is no ramp down). The valid 1−6 outputs are immediately asserted low and the PWM outputs

are placed in the hard mute state. PDN initiates device power down without clock inputs. As long as the PDN

terminal is held low, the device is in the power-down (hard mute) state.

During power down, all I2C and serial data bus operations are ignored. Table 2−8 shows the device output

signals while PDN is active.

Table 2−8. Device Outputs During Power Down

SIGNAL

MODE

SIGNAL STATE

Valid 1−Valid 6

All

Low

PWM_P outputs

All

Low

PWM_M outputs

All

Low

MCLK_OUT

All

Low

SCLK

Master

Low

SCLK

Slave

Signal input

LRCLK

Master

Low

LRCLK

Slave

Signal input

SDA

All

Signal input

CLIP

All

High

To place the device in total power-down mode, both RESET and power-down modes must be enabled. Prior

to bringing PDN high, RESET must be brought low for a minimum of 50 ns.

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