TAS5036AIPFCR datasheet(28/62 Pages) TI

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Architecture Overview

SLES061B—November 2002—Revised January 2004

TAS5036A

2.4.4 PWM DC-Offset Correction

An 8-bit value can be programmed to each of the six PWM offset correction registers to correct for any offset

present in the output stages. The offset correction is divided into 256 intervals with a total offset correction of

±1.56% of full scale. The default value is zero correction represented by 00h. These values can be changed

at any time through the serial control interface.

2.4.5 Interchannel Delay

An 8-bit value can be programmed to each of the six PWM interchannel delay registers to add a delay per

channel from 0 to 255 clock cycles. The delays correspond to cycles of the high-speed internal clock, DCLK.

Each subsequent channel has a default value that is N DCLKs larger than the preceding channel. The default

values are 0 for the first channel and 76 for each successive channel.

These values can be updated upon power up through the serial control interface. This delay is generated in

the PWM block with the appropriate control signals generated in the CTL block.

These values can be changed at any time through the serial control interface.

2.4.6 ABD Delay

A 5-bit value is used to delay the A PWM signals with respect to B PWM signals. The value is the same for

all channels. It can be programmed from 0 to 31 DCLK clock cycles. The default value is 17 DCLK clock cycles

(01011). These values can be changed at any time through the serial control interface.

NOTE:

The performance of a PurePath Digital

 amplifier system is optimized by setting the PWM

timing based upon the type of back-end device that is used and the layout. These values are

set during initialization using the I2C serial interface.

2.4.7 PWM/H-Bridge and Discrete H-Bridge Driver Interface

The TAS5036A provides six PWM outputs, which are designed to drive switching output stages (back-ends)

in both single-ended (SE) and H-bridge (bridge-tied load) configuration. The back ends can be monolithic

power stages (such as the TAS5110) or six discrete differential power stages using gate drivers (such as the

the TAS55182) and MOSFETs in single-ended or bridged configurations.

The TAS5110 device is optimized for bridge-tied load (BTL) configurations. These devices require a pure

differential PWM signal with a third signal (VALID) to control the MUTE state. In the MUTE state, the TAS5110

OUTA and OUTB are both low.

One Channel

of TAS5036A

PWM_AP

PWM_AM

VALID

TAS5110

OUTA

OUTB

RESET

Speaker

Figure 2−12. PWM Outputs and H-Bridge Driven in BTL Configuration

2.5

I2C Serial Control Interface

MCLK must be active for the TAS5036A to support I2C bus transactions. The TAS5036A has a bidirectional

serial control interface that is compatible with the I2C (Inter IC) bus protocol and supports both 100-kbps and

400-kbps data transfer rates for single- and multiple-byte write and read operations. This is a slave-only device

that does not support a multi-master bus environment or wait state insertion. The control interface is used to

program the registers of the device and to read device status.

PurePath Digital is a trademark of Texas Instruments.

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