AD8021 datasheet(6/32 Pages) AD

6 / 32 page

AD7952

Rev. 0 | Page 6 of 32

Parameter

Symbol

Min

Typ

Max

Unit

SLAVE SERIAL/SERIAL CONFIGURATION INTERFACE MODES2

(See Figure 43, Figure 44, and Figure 46)

External SDCLK, SCCLK Setup Time

t31

External SDCLK Active Edge to SDOUT Delay

t32

SDIN/SCIN Setup Time

t33

SDIN/SCIN Hold Time

t34

External SDCLK/SCCLK Period

t35

External SDCLK/SCCLK High

t36

External SDCLK/SCCLK Low

t37

1 In warp mode only, the time between conversions is 1 ms; otherwise, there is no required maximum time.

2 In serial interface modes, the SYNC, SDSCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.

3 In serial master read during convert mode. See Table 4 for serial master read after convert mode.

Table 4. Serial Clock Timings in Master Read After Convert Mode

DIVSCLK[1]

DIVSCLK[0]

Symbol

Unit

SYNC to SDCLK First Edge Delay Minimum

t18

Internal SDCLK Period Minimum

t19

120

240

Internal SDCLK Period Maximum

t19

180

360

Internal SDCLK High Minimum

t20

120

Internal SDCLK Low Minimum

t21

115

SDOUT Valid Setup Time Minimum

t22

SDOUT Valid Hold Time Minimum

t23

SDCLK Last Edge to SYNC Delay Minimum

t24

BUSY High Width Maximum

t28

Warp Mode

1.60

2.35

3.75

6.75

μs

Normal Mode

1.85

2.60

4.00

7.00

μs

Impulse Mode

2.10

2.85

4.25

7.25

μs

NOTES

1. IN SERIAL INTERFACE MODES, THE SYNC, SDCLK, AND

SDOUT ARE DEFINED WITH A MAXIMUM LOAD

CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.

1.6mA

IOL

500µA

IOH

1.4V

TO OUTPUT

60pF

Figure 2. Load Circuit for Digital Interface Timing,

SDOUT, SYNC, and SDCLK Outputs, CL = 10 pF

0.8V

tDELAY

Figure 3. Voltage Reference Levels for Timing

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