UPD98409 datasheet(13/42 Pages) RENESAS

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Data Sheet S12775EJ4V0DS

µPD98409

1.4 JTAG Boundary Scan Pins

(These functions can be supported by request.)

Pin Name

Pin No.

I/O

I/O Level

Function

JDI

216

LV-TTL

JTAG Test Data Input.

The JDI pin is used to input data to the JTAG boundary scan circuit

Normally, fix this pin to high or low level.

JDO

217

3-state

TTL

JTAG Test Data Output.

The JDO pin is used to output data from the JTAG boundary scan

circuit register. It changes output at the falling edge of the clock input

to the JCK pin.

Normally, leave this pin open.

JCK

214

LV-TTL

JTAG Test Clock.

This pin is used to supply a clock to the JTAG boundary scan circuit

Normally, fix this pin to a high or low level.

JMS

218

LV-TTL

JTAG Test Mode Select.

Normally, fix this pin to a high or low level.

JRST_B

219

LV-TTL

JTAG Test Reset.

This pin initializes the JTAG boundary scan circuit register. Normally,

fix this pin to a low level.

Remark

Processing of JTAG boundary scan pins not used (during normal operation)

The reason that the JRST_B pin is grounded when it is not used (during normal operation) is to better

prevent malfunctioning of the JTAG logic. The JTAG pin may be also processed in either of the

following ways:

• Reset the JTAG logic without using the JRST_B pin

Reset the JTAG logic by using the JMS and JCK pins and keep it in the reset status (the JRST_B

pin is pulled up).

Fix the JMS pin to 1 (pull up) and input 5 clock cycles or more to the JCK pin.

• Reset the JTAG logic by using the JRST_B pin

Input a low pulse of the same width as RST_B of the

µPD98409 to the JRST_B pin. If both the JMS

and JRST_B pins are pulled up and kept high, the JTAG logic is not released from the reset status.

Therefore, the normal operation is not affected. Fix the input level of the JDI and JCK pins by

pulling them down or up.

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