UPD77533 datasheet(83/104 Pages) RENESAS

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Data Sheet S15671EJ4V0DS

µµµµPD77533

20. APPLICATION CIRCUIT EXAMPLE

RXD

RTS

CTS

TXD

REFCLK

TXACTV

RESETB

WKUPB

STNDBYB

INVRX

MCSB

MRDB

MWRB

MA19 to MA0

MD15 to MD0

RFON

AGC

DCOFF

ADDI3 to ADDI0

(4 bits of MSBs are used.)

ADSCK

GPSCLK

PD77533

Host

CPU

PDC

module

(10 to 20 MHz)

Power

supply

RF block power

supply control

VCC

PD4616112

ADC

PB1007

RF blockNote

1575.42 MHz

TCXO

16.384 MHz

/CS

/OE

/WE

A19 to A0

I/O15 to I/O0

Mobile specified RAM

RF/IF frequency down converter + PLL frequency synthesizer IC

VGC (IF-MIX)

REFin1

2ndIFout

Caution The system gain of the

µµµµPD77533 is 60.1 dB.

Note The following shows the recommended operation environment for the GPS signal input portion (RF block)

to the

µPD77533.

Parameter

Value

Accuracy of input clock to REFCLK

±0.1 ppm

Local oscillator stability

Accuracy of input clock to GPSCLK

Not used

Resolution of A/D converter

4 bits or more

Conversion speed of A/D converter

8.192 MHz

System NF

< 2 dB

In-band supurious

In the band of the center frequency of the last IF signal

±1 MHz, the total power of

supurious should be less

−20 dBc with reference to the IF noise level.

Average antenna gain

−6 dBi or more (linear)

If the recommended accuracy of the local oscillator stability cannot be obtained, it is possible to use the FCC

function via REFCLK (refer to 6.1 FCC Function). In this case, however, the positioning time and sensitivity may be

degraded.

An example is shown below (in this example, the positioning time is approximately 30 seconds max., and the

sensitivity is hardly degraded at all).

Accuracy of input clock to REFCLK: <

±0.3 ppm

Accuracy of input clock to GPSCLK: <

±10 ppm

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