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t

BCH

t

BCL

t

BCDO

t

BCY

BCKO

(OUT)

LRCKO

(OUT)

DOUT

(OUT)

SCKO

(OUT)

V

/2

DD

t

CKLR

t

SCBC

t

SCY

V

/2

DD

V

/2

DD

V

/2

DD

DIR9001

SLES198 – DECEMBER 2006

PARAMETERS

MIN

TYP

MAX

UNIT

System clock pulse cycle time

18

ns

Delay time of SCK rising edge to BCK rising edge

4

8

15

ns

Delay time of BCKO falling edge to LRCKO valid

–5

0.5

0.5

ns

BCKO pulse cycle time

s

BCKO pulse duration, HIGH

60

ns

BCKO pulse duration, LOW

60

ns

Delay time of BCKO falling edge to DOUT valid

–5

1

5

ns

Rising time of all signals

10

ns

Falling time of all signals

10

ns

NOTE: Load capacitance of the LRCKO, BCKO, and DOUT pins is 20 pF. DOUT, LRCKO, and BCKO are synchronized with

SCKO.

Figure 12. Decoded Audio Data Output Timing

19

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