M41T93RMY6F datasheet(12/49 Pages) STMICROELECTRONICS

12 / 49 page

Operation

M41T93

12/49

Operation

The M41T93 clock operates as a slave device on the SPI serial bus. Each memory device is

accessed by a simple serial interface that is SPI bus-compatible. The bus signals are SCL,

SDI, and SDO (see Table 1 on page 7 and Figure 5 on page 10). The device is selected

when the Chip Enable input (E) is held low. All instructions, addresses and data are shifted

serially in and out of the chip. The most significant bit is presented first, with the data input

(SDI) sampled on the first rising edge of the clock (SCL) after the Chip Enable (E) goes low.

The 32 bytes contained in the device can then be accessed sequentially in the following

order:

The M41T93 clock continually monitors VCC for an out-of tolerance condition. Should VCC

fall below VRST, the device terminates an access in progress and resets the device address

counter. Inputs to the device will not be recognized at this time to prevent erroneous data

from being written to the device from a an out-of-tolerance system.

The power input will also be switched from the VCC pin to the external battery when VCC falls

below the battery back-up switchover voltage (VSO = VRST). At this time the clock registers

will be maintained by the battery supply. As system power returns and VCC rises above VSO,

the battery is disconnected, and the power supply is switched to external VCC.

Write protection continues until VCC reaches VPFD (min) plus tREC (min). For more

information on Battery Storage Life refer to Application Note AN1012.

Tenths/hundredths of a second register

Seconds register

Minutes register

Century/hours register

Day register

Date register

Month register

Year register

Digital calibration register

Watchdog register

11-15

Alarm1 registers

Flags register

Timer value register

Timer control register

Analog calibration register

Square wave register

21-25

Alarm2 registers

26-32

User RAM

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