ST7L15 datasheet(105/138 Pages) STMICROELECTRONICS

105 / 138 page

ST7L15, ST7L19

105/138

OPERATING CONDITONS (cont’d)

13.3.2 Operating Conditions with Low Voltage Detector (LVD)

TA = -40 to +125°C, unless otherwise specified.

Notes:

1. LVD functionality guaranteed only within the VDD operating range specified in section 13.3.1 on page 100.

2. Not tested in production.

3. Not tested in production. The VDD rise time rate condition is needed to insure a correct device power-on and LVD reset.

When the VDD slope is outside these values, the LVD may not ensure a proper reset of the MCU.

4. Based on design simulation.

5. Use of LVD with capacitive power supply: With this type of power supply, if power cuts occur in the application, it is rec-

ommended to pull VDD down to 0V to ensure optimum restart conditions. Refer to circuit example in Figure 95 on

page 119 and note 4.

13.3.3 Internal RC Oscillator and PLL

The ST7 internal clock can be supplied by an internal RC oscillator and PLL (selectable by option byte).

Notes:

1. x4 PLL option only applicable on Flash devices.

Symbol

Parameter

Conditions1)

Min

Typ

Max

Unit

VIT+(LVD)

Reset release threshold (VDD rise)

3.802)

4.20

4.60

VIT-(LVD)

Reset generation threshold (VDD fall)

3.70

4.00

4.352)

Vhys

LVD voltage threshold hysteresis

VIT+(LVD)-VIT-(LVD)

200

VtPOR

VDD rise time rate

3)5)

0.022)

1002)

ms/V

tg(VDD)

Filtered glitch delay on VDD

Not detected by the LVD

1504)

IDD(LVD)

LVD current consumption

200

µA

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VDD(RC)

Internal RC oscillator operating voltage

Refer to operating range

of VDD with TA, section

13.3.1 on page 100

3.0

5.5

VDD(x4PLL)

x4 PLL operating voltage1)

3.0

3.6

VDD(x8PLL)

x8 PLL operating voltage

3.6

5.5

tSTARTUP

PLL Start-up time

PLL

input

clock

(fPLL)

cycles

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