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ST7L15 датащи(PDF) 102 Page - STMicroelectronics |
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ST7L15 датащи(HTML) 102 Page - STMicroelectronics |
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102 / 138 page ![]() ST7L15, ST7L19 102/138 OPERATING CONDITIONS (cont’d) Figure 62. fRC vs VDD and Temperature for Calibrated RCCR0 13.3.1.2 Operating Conditions (tested for TA = -40 to +125°C) @ VDD = 3.0 to 3.6V 1) Notes: 1. Data based on characterization results, not tested in production. 2. If the RC oscillator clock is selected, to improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device. 3. See “INTERNAL RC OSCILLATOR ADJUSTMENT” on page 21. 4. Minimum value is obtained for hot temperature and maximum value is obtained for cold temperature. 5. Measurement made with RC calibrated at 1 MHz. 6. Guaranteed by design. 7. Averaged over a 4ms period. After the LOCKED bit is set, a period of tSTAB is required to reach ACCPLL accuracy. 8. After the LOCKED bit is set, ACCPLL is maximum 10% until tSTAB has elapsed. See Figure 11 on page 22. Symbol Parameter1) Conditions Min Typ Max Unit fRC 2) Internal RC oscillator fre- quency RCCR = FF (reset value), TA = 25°C, VDD = 3.3V 700 kHz RCCR = RCCR13), TA = 25°C, VDD = 3.3V 992 1000 1008 ACCRC Accuracy of Internal RC oscillator when calibrated with RCCR = RCCR13)4) TA = 25°C, VDD = 3.3V -0.8 +0.8 % TA = 25°C, VDD = 3 to 3.6V -1 +1 TA= -40 to +125°C, VDD = 3 to 3.6V -5 +6.5 IDD(RC) RC oscillator current con- sumption TA = 25°C, VDD = 3.3V 4005) µA tsu(RC) RC oscillator setup time TA = 25°C, VDD =3.3V 103) µs fPLL x4 PLL input clock 0.7 MHz tLOCK PLL lock time8) 2 ms tSTAB PLL stabilization time8) 4 ACCPLL x4 PLL accuracy fRC = 1 MHz @ TA = -40 to +125°C, VDD = 3.3V 0.17) % fRC =1 MHz @ TA = 25°C, VDD = 3 to 3.6V 0.17) JITPLL PLL jitter ( ∆f CPU/fCPU)1 6) IDD(PLL) PLL current consumption TA = 25°C 190 µA 0.98 0.985 0.99 0.995 1 1.005 1.01 1.015 1.02 1.025 4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5 Vdd (V) -45 -10 0 25 90 110 130 |
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