Philips Semiconductors

Product specification

TrenchMOS

™ transistor

PHT8N06LT

Logic level FET

GENERAL DESCRIPTION

QUICK REFERENCE DATA

N-channel enhancement mode logic

SYMBOL

PARAMETER

MAX.

UNIT

level field-effect power transistor in a

plastic envelope suitable for surface

V

DS

Drain-source voltage

55

V

mounting. The device features very

I

D

Drain current

7.5

A

low on-state resistance and has

P

tot

Total power dissipation

1.8

W

integral zener diodes giving ESD

T

j

Junction temperature

150

˚C

protection. It is intended for use in

R

DS(ON)

Drain-source on-state

80

m

Ω

DC-DC

converters

and

general

resistance

V

GS = 5 V

purpose switching applications.

PINNING - SOT223

PIN CONFIGURATION

SYMBOL

PIN

DESCRIPTION

1

gate

2

drain

3

source

4

drain (tab)

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V

DS

Drain-source voltage

-

-

55

V

V

DGR

Drain-gate voltage

R

GS = 20 kΩ

-55

V

±V

GS

Gate-source voltage

-

-

13

V

I

D

Drain current (DC)

T

sp = 25 ˚C

-

7.5

A

I

D

Drain current (DC)

On PCB in Fig.2

-

3.5

A

T

amb = 25 ˚C

I

D

Drain current (DC)

On PCB in Fig.2

-

2.2

A

T

amb = 100 ˚C

I

DM

Drain current (pulse peak value)

T

sp = 25 ˚C

-

40

A

P

tot

Total power dissipation

T

sp = 25 ˚C

-

8.3

W

P

tot

Total power dissipation

On PCB in Fig.2

-

1.8

W

T

amb = 25 ˚C

T

stg, Tj

Storage & operating temperature

-

- 55

150

˚C

ESD LIMITING VALUE

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V

C

Electrostatic discharge capacitor

Human body model

-

2

kV

voltage

(100 pF, 1.5 k

Ω)

d

g

s

4

1

23

January 1998

1

Rev 1.100