Philips Semiconductors

Product specification

TrenchMOS

™ transistor

PHT6N06LT

Logic level FET

GENERAL DESCRIPTION

QUICK REFERENCE DATA

N-channel enhancement mode

SYMBOL

PARAMETER

MAX.

UNIT

logic level field-effect power

transistor in a plastic envelope

V

DS

Drain-source voltage

55

V

suitable for surface mounting.

I

D

Drain current (DC) T

sp = 25 ˚C

5.5

A

The device features very low

Drain current (DC) T

amb = 25 ˚C

2.5

A

on-state resistance and has

P

tot

Total power dissipation

8.3

W

integral zener diodes giving

T

j

Junction temperature

150

˚C

ESD protection. It is intended for

R

DS(ON)

Drain-source on-state

150

m

Ω

use in DC-DC converters and

resistance

V

GS = 5 V

general

purpose

switching

applications.

PINNING - SOT223

PIN CONFIGURATION

SYMBOL

PIN

DESCRIPTION

1

gate

2

drain

3

source

4

drain (tab)

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V

DS

Drain-source voltage

-

-

55

V

V

DGR

Drain-gate voltage

R

GS = 20 kΩ

-55

V

V

GS

Gate-source voltage

-

-

±13

V

I

D

Drain current (DC)

T

sp = 25 ˚C

-

5.5

A

T

amb = 25 ˚C

-

2.5

A

I

D

Drain current (DC)

T

sp = 100 ˚C

-

3.8

A

T

amb = 100 ˚C

-

1.75

A

I

DM

Drain current (pulse peak value)

T

sp = 25 ˚C

-

22

A

T

amb = 25 ˚C

-

10

A

P

tot

Total power dissipation

T

sp = 25 ˚C

-

8.3

W

T

amb = 25 ˚C

-

1.8

W

T

stg, Tj

Storage & operating temperature

-

- 55

150

˚C

ESD LIMITING VALUE

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V

C

Electrostatic discharge capacitor

Human body model

-

2

kV

voltage

(100 pF, 1.5 k

Ω)

d

g

s

4

1

23

January 1998

1

Rev 1.100