HT46R342 datasheet(9/40 Pages) HOLTEK

9 / 40 page

HT46R322/HT46R342

Rev. 1.00

December 21, 2006

in the ISR. In such a case errors can occur. Therefore,

using the table read instruction in the main routine and

the ISR simultaneously should be avoided. However,

if the table read instruction has to be used in both the

main routine and the ISR, the interrupt is should be

disabled prior to the table read instruction. It should

not be re-enabled until the TBLH has been backed up.

All table related instructions require two cycles to

complete their operation. These areas may function

as normal program memory depending upon require-

ments.

Stack Register

- STACK

This is a special part of the memory which is used to

save the contents of the program counter only. The

stack is organized into 6 levels and is neither part of the

data nor part of the program space, and is neither read-

able nor writeable. The activated level is indexed by the

stack pointer, known as stack pointer, and is also neither

readable nor writeable. At a subroutine call or interrupt

acknowledgment, the contents of the program counter

are pushed onto the stack. At the end of a subroutine or

an interrupt routine, signaled by a return instruction,

RET or RETI, the program counter is restored to its pre-

vious value from the stack. After a device reset, the

stack pointer will point to the top of the stack.

If the stack is full and a non-masked interrupt takes

place, the interrupt request flag will be recorded but the

acknowledgment will be inhibited. When the stack

pointer is decremented, using a RET or RETI instruc-

tion, the interrupt will be serviced. This feature prevents

a stack overflow allowing the programmer to use the

structure more easily. In a similar case, if the stack is full

and a

²CALL² is subsequently executed, stack overflow

occurs and the first entry will be lost. Only the most re-

cent 6 return addresses are stored.

Data Memory

- RAM

The data memory has a structure of 115

´8 bits for the

HT46R322 device and 219

´8 bits for the HT46R342

device. The data memory is divided into two functional

groups: special function registers and general purpose

data memory. The general purpose memory has a

structure of 88

´8 bits for the HT46R322 device and

192bits

´8 bits for the HT46R342 device. Most loca-

tions are read/write, but some are read only.

The remaining space between the end of the Special

Purpose Data Memory and the beginning of the General

Purpose Data Memory is reserved for future expanded

usage, reading these locations will obtain a result of

²00H². The general purpose data memory, addressed

from 28H to 7FH in the HT46R322, and from 40H to FFH

in the HT46R342, is used for user data and control infor-

mation under instruction commands. All of the data

memory areas can handle arithmetic, logic, increment,

decrement and rotate operations directly. Except for

some dedicated bits, each bit in the data memory can

be set and reset by the

²SET [m].i² and ²CLR [m].i² in-

structions. They are also indirectly accessible through

memory pointer register, MP.

Indirect Addressing Register

Location 00H is an indirect addressing register that is

not physically implemented. Any read/write operation on

[00H] accesses data memory pointed to by the MP

the result 00H. Writing indirectly results in no operation.

For the HT46R322 device the memory pointer register,

MP, is a 7-bit register, while for the HT46R342 device it

is an 8-bit register. For the HT46R322 device, bit 7 of

MP is undefined and if read will return the result

²1², any

write operation will only transfer the lower 7-bits of data to

MP.

Accumulator

The accumulator is closely related to ALU operations

and can carry out immediate data operations. Any data

movement between two data memory locations must

pass through the accumulator.

S p e c i a l P u r p o s e

D a t a M e m o r y

0 0 H

0 1 H

0 2 H

0 3 H

0 4 H

0 5 H

0 6 H

0 7 H

0 8 H

0 9 H

0 A H

0 B H

0 C H

0 D H

0 E H

0 F H

1 0 H

1 1 H

1 2 H

1 3 H

1 4 H

1 5 H

1 6 H

1 7 H

1 8 H

1 9 H

1 A H

1 B H

1 C H

1 D H

1 E H

1 F H

I n d i r e c t A d d r e s s i n g R e g i s t e r

M P

A C C

P C L

T B L P

T B L H

S T A T U S

I N T C

T M R

T M R C

P A

P A C

P B

P B C

P C

P C C

P D

P D C

P E

P E E

P W M 0

P W M 1

O P A C

A D R L

A D R H

A D C R

A C S R

: U n u s e d

R e a d a s " 0 0 "

2 0 H

2 1 H

2 2 H

2 3 H

2 7 H

2 4 H

G e n e r a l P u r p o s e

D a t a M e m o r y

( 8 8 B y t e s )

7 F H

2 8 H

3 9 H

2 4 H

G e n e r a l P u r p o s e

D a t a M e m o r y

( 1 9 2 B y t e s )

F F H

4 0 H

H T 4 6 R 3 2 2

H T 4 6 R 3 4 2

H T 4 6 R 3 2 2 / H T 4 6 R 3 4 2

RAM Mapping

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