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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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WM8750BL датащи(PDF) 39 Page - Wolfson Microelectronics plc |
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WM8750BL датащи(HTML) 39 Page - Wolfson Microelectronics plc |
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39 / 59 page  Pre-Production WM8750BL w Pre-Production Rev 3.3 January 2007 39 In DSP/PCM mode, the left channel MSB is available on either the 1 st (mode B) or 2nd (mode A) rising edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample. In device master mode, the LRC output will resemble the frame pulse shown in Figure 20 and Figure 21. In device slave mode, Figure 22 and Figure 23, it is possible to use any length of frame pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period before the rising edge of the next frame pulse. Figure 20 DSP/PCM Mode Audio Interface (mode A, LRP=0, Master) Figure 21 DSP/PCM Mode Audio Interface (mode B, LRP=1, Master) |
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